PXIe-6674T Specifications - National Instruments

1 SPECIFICATIONSPXIe-6674 TTiming and Synchronization Module for PXI ExpressThis appendix lists the system Specifications for PXIe-6674T modules. These specificationsare typical at 25 C, unless otherwise Specifications are subject to change without Some Specifications are specific to earlier revisions of the PXIe-6674 Tmodule. A label with revision information can be found on the module board asshown in Figure 1. on page denotes all letter revisions of the assembly. Ensure the Specifications of interest match therevision that is printed on the 1. PXIe-6674T Revision LabelCOOPXIe-667I99223D-0 ILI99225D-0 ICRI99223D-0 ILS/NDefinitionsWarranted Specifications describe the performance of a model under stated operatingconditions and are covered by the model following characteristic Specifications describe values that are relevant to the use of themodel under stated operating conditions but are not covered by the model warranty.

2 Typical Specifications describe the performance met by a majority of models. Nominal Specifications describe an attribute that is based on design, conformance testing,or supplemental are Typical unless otherwise Specifications ConditionsSpecifications are valid at 25 C unless otherwise GuidelinesCaution This icon denotes a caution, which advises you to consult documentationwhere this symbol is Do not operate the PXIe-6674T in a manner not specified in thisdocument. Product misuse can result in a hazard. You can compromise the safetyprotection built into the product if the product is damaged in any way. If the productis damaged, return it to NI for You can impair the protection provided by the PXIe-6674T if you use it ina manner not described in this CharacteristicsInput couplingACInput impedance50 , nominalSettingAttenuation Setting OnAttenuation SettingOff Attenuation SettingOn (default)OffAttenuation Behavior5:11:1 Minimum Input Swing with 50% DutyCycle1750 mVpp150 mVpp1A duty cycle other than 50% will increase the minimum input swing.

3 Refer to Maximum andMinimum Input Swing with Attenuation On for more | | PXIe-6674T SpecificationsSettingAttenuation Setting OnAttenuation SettingOff Maximum Input Swing with 50% VppAbsolute Maximum Input Powered VppAbsolute Maximum Input Powered Off VppNote Input can be either square wave or 2. Maximum and Minimum Input Swing with Attenuation Swing (Vpp)Input Duty Cycle (%)Minimum Input Swing (Vpp)Maximum Input Swing (Vpp)01020304050607080901002A duty cycle other than 50% will increase the minimum input swing. Refer to Maximum andMinimum Input Swing With Attenuation Off for more above the Absolute Maximum Input Powered On may cause damage to the Maximum Input Powered Off is the maximum input signal amplitude that the device cantolerate before damage might occur while in an unpowered Specifications | National Instruments | 3 Figure 3.

4 Maximum and Minimum Input Swing With Attenuation Swing VppInput Duty CycleMinimum Input Swing (Vpp)Maximum Input Swing (Vpp)Minimum Frequency1 MHz5 Maximum FrequencyTo Clk10 PLL100 MHzTo FPGA200 MHzTo PXIe-DStarA1 GHzClkIn to PXI_Clk10_In Delay (PLL not used)Typical at 25 nsMaximum over nsOCXON ominal Frequency10 MHzAccuracy within 1 year of calibrationadjustment within 0 C to 55 C operatingtemperature range 6 80 ppbLong-term stability 50 ppb/yearStability vs temperature<10 ppb peak-to-peak within 0 C to 55 Coperating temperature range5 The minimum frequency is limited by AC 72 hours of continuous | | PXIe-6674T SpecificationsTuning Range ppm minimum, 2 ppm typical, 4 ppmmaximumTuning DAC Resolution16 bits, ppb per step typicalRecommended calibration interval1 yearTable 1. Maximum Phase Noise of the OCXOO ffsetPhase Noise 1 Hz-80 dBc/Hz10 Hz-120 dBc/Hz100 Hz-140 dBc/Hz1 kHz-145 dBc/Hz10 kHz-150 dBc/HzFigure 4.

5 On page 6 shows the phase noise on a representative module. OCXO is routed tothe ClkOut SMA, measured in a NI PXIe-1082 chassis with low fan speed7. The integratedjitter from 10 Hz to 1 MHz is 507 fs also driven to Specifications | National Instruments | 5 Figure 4. Phase Noise on a Representative Module with OCXO Routed to ClkOut SMA 1601002 MdBc/HzFrequency Offset (Hz)10k100k1M1k 801 155 150 135 130 145 140 125 120 115 110 100 95 90 85 10510 Figure 5. on page 7 shows the phase noise on a representative module of PXI_CLK10 whenOCXO is routed to PXI_CLK10_IN,8 measured in a NI PXIe-1082 chassis with low fanspeed:8 The PXIe backplane employs a PLL to phase lock PXI_CLK10 to the signal on a result, the phase noise of PXI_CLK10 above about 1 kHz offset is unchanged, regardless ofreference | | PXIe-6674T SpecificationsFigure 5.

6 Phase Noise on a Representative Module of PXI_CLK10 when OCXO isrouted to PXI_CLK10_IN1002 MdBc/HzFrequency Offset (Hz)10k100k1M1k 501 160 155 150 135 130 145 140 125 120 115 110 100 65 70 75 80 85 90 95 60 55 10510A. PXI_CLK10 with no reference usedB. NI PXIe-6674T OCXO at PXI_CLK10_INC. Resulting PXI_CLK10 with OCXO routed to PXI_CLK10_INABC10 MHz PLLR eference Frequency Range (from ClkIn)1 MHz to 100 MHz, in increments of 1 MHzRecommended ClkIn Frequency910 MHzReference Frequency Required Accuracy ppmReference Frequency Duty Cycle40% to 60%PLL Loop Bandwidth100 HzMaximum PXI_CLK10 Phase Offset+/- 1 ns910 MHz PLL filter is designed for a 10 MHz phase detector frequency. Any other referencefrequency will default to a phase detector frequency of 1 MHz resulting in a slight degradation ofPLL Specifications | National Instruments | 7 Figure 6.

7 On page 8 shows the phase noise on a representative module of PXI_CLK10 whenCLKIN is routed to PXI_CLK10_IN with and without the 10 MHz PLL, measured in a NIPXIe-1082 chassis with low fan 6. Phase Noise on a Representative Module of PXI_CLK10 with CLKIN Routingto PXI_CLK10_IN1002 MdBc/HzFrequency Offset (Hz)10k100k1M1k 501 160 155 150 135 130 145 140 125 120 115 110 100 65 70 75 80 85 90 95 60 55 10510A. PXI_CLK10 with no reference usedB. Reference from CLKIN at PXI_CLK10_IN (10 MHz PLL not used)C. Resulting PXI_CLK10 with CLKIN routed to PXI_CLK10_IN (10 MHz PLL not used)D. Resulting PXI_CLK10 with 10 MHz PLL used1002 MdBc/HzFrequency Offset (Hz)10k100k1M1k 501 160 155 150 135 130 145 140 125 120 115 110 100 65 70 75 80 85 90 95 60 55 10510A. PXI_CLK10 with no reference usedB. Reference from CLKIN at PXI_CLK10_IN (10 MHz PLL not used)C.

8 Resulting PXI_CLK10 with CLKIN routed to PXI_CLK10_IN (10 MHz PLL not used)D. Resulting PXI_CLK10 with 10 MHz PLL usedABCDClkOutLow Speed ClkOutHigh Speed ClkOut CouplingAC CoupledAC CoupledExpected Termination50 or high impedance50 10 The PXIe backplane employs a PLL to phase lock PXI_CLK10 to the signal on a result, the phase noise of PXI_CLK10 above about 1 kHz offset is unchanged, regardless ofreference | | PXIe-6674T SpecificationsLow Speed ClkOutHigh Speed ClkOut Frequency Range1 MHz to 50 MHz111 MHz to 1 GHz12 Typical Vpp into 50 , 5 Vpp into highZ800 mVppRising/Falling Edge (20%,80%)270 ps, typical180 ps, typicalDuty Cycle of output withClock Generation as source45% to 55%45% to 55%Available SourcesPXI_CLK10, 10 MHz OCXO,Clock Generation up to 50 MHzClock Generation, PXIe-DStarA Network13 PXI_CLK10 to ClkOut DelayTypical at 25 nsMaximum over nsFigure 7.

9 On page 9 shows the typical Low Speed ClkOut Amplitude performance, with asample size of 19 7. Typical Low Speed ClkOut Amplitude PerformanceAmplitude (Vpp)Frequency (MHz) 8. on page 10 shows the typical High Speed ClkOut Amplitude performance, with asample size of 19 of low speed ClkOut above 50 MHz is possible however NI does not guaranteeperformance. Use ClkOutLS as the destination terminal to force NI-Sync to use the low speeddriver above 50 above 1 GHz is possible but NI does not guarantee PXIe-DStarA to ClkOut requires routing through either Banks 0, 1, or Specifications | National Instruments | 9 Figure 8. Typical High Speed ClkOut Amplitude PerformanceAmplitude (Vpp)Frequency (MHz) GenerationReference Frequency Source14 PXIe_Clk100 Base Frequency Resolution (150 MHz to300 MHz) Hz15 Minimum Generated Frequency16 With FPGA HzWithout FPGA MHzMaximum Generated Frequency1 GHz17 Clock Generation Phase Noise PerformanceNote All Phase Noise Measurements were made on a Representative Module ofvarious Clock Generation frequencies routed to ClkOut.

10 All measurements made in14 Frequency Accuracy is inherited from PXIe_Clk100/PXI_Clk10. Use OCXO for PXIe_Clk100/PXI_Clk10 replacement for improved frequency accuracy and phase is the frequency resolution of the DDS used in the Clock Generation circuitry. For ClockGeneration frequencies below 150 MHz, this resolution is divided down and for frequencies above300 MHz, this resolution is multiplied routed to ClkOut Low Speed or used as a trigger synchronization clock, Clock Generationcan be further divided by theFPGA by factors of two up to 24. This extends the Clock Generationrange down to MHz/224=.2794 Hz. When routed to ClkOut High Speed the minimumfrequency is MHz. Use ClkOutHS as the destination terminal to force NI-Sync to use thelow speed driver below 50 MHz. Note that AC coupling on ClkOut limits the minimum frequencywhich can be Generation can be operated beyond the upper limit; however, NI does not guaranteeperformance beyond 1 GHz.