Single-Chip HDMI Receiver Port Protection and Interface ...

1 Core ScalarChipD3-GNDD3+D2-GNDD2+D1-GNDD1+D0- GNDD0+HTP_D5 VGNDD_DATD_CLKNCCE_R5 V5 uF5 VVLVVLVVLVVLVVLVVLV100 kW47 kW47 kW47 kW47 kW47 kW1 kW27 kW10 kWHPD_INDDAT_INDCLK_INCEC_INHPD_OUTDDAT_ OUTDCLK_OUTCEC_OUTLV_SUPPLY5V_SUPPLYESD_ BYPNCP roductFolderSample &BuyTechnicalDocumentsTools &SoftwareSupport &CommunityTPD12S520 SLVS640F OCTOBER2007 REVISEDFEBRUARY2015 TPD12S520 Single-ChipHDMI ReceiverPort Protectionand InterfaceDevice1 Features3 DescriptionTheTPD12S520is a single-chipelectro-static1 IEC 61000-4-2 Level4 ESDP rotectiondischarge(ESD)circuitprotection devicefor the high- 8-kVContactDischargeon ExternalLinesdefinitionmultimediainterfa ce( hdmi )receiverport. Single-ChipESDS olutionfor HDMID riverWhileprovidingESDprotectionwith transientvoltagesuppression(TVS)diodes,t he TVSprotectionadds 12 ChannelESDP rotectionDiodeslittleor no additionalglitchin thehigh-speed SupportsAll and ( 3 dB Frequency> 3 GHz)minimizeddifferentialsignaling(TMDS) ESD the HighSpeedTMDS protectionlinesadd only low-speedcontrollinesoffervoltage-levels hifting eliminatethe needfor an externalvoltagelevel-DifferentialSignalP airshifterIC.

2 Thecontrolline TVSdiodesadd the 38-PinTSSOPP rovidesSeamlessLayoutOptionpackageoffers a seamlesslayoutroutingoptiontowith HDMIC onnectoreliminatethe routingglitchfor the differentialsignal 24-PinWQFNP ackagefor DBTpackagepitch( mm) addition,thepin BackdriveProtectionmappingfollowsthesame orderas theHDMI connectorpin Lead-FreePackageprotectionandinterfacede viceis designedspecificallyfor ApplicationsThe 24-pinRMNpackageoffersflow throughrouting VideoInterfaceusingonlytwo layersfor highlyintegrated,space-efficientfull hdmi Protection . ConsumerElectronics Displaysand DigitalTelevisionsDeviceInformation(1) HandheldDisplaysDEVICENAMEPACKAGEBODYSIZ E(NOM)TSSOP(38) (24) (1) For all availablepackages,see the orderableaddendumatthe end of the IMPORTANTNOTICEat the end of this datasheetaddressesavailability,warranty, changes,use in safety-criticalapplications,intellectual propertymattersand OCTOBER2007 Applicationand Pin Configurationand Deviceand Mechanical,Packaging,and RevisionHistoryChangesfromRevisionE (September2014)to RevisionFPage Addedclarificationto Addedclarificationto (December2013)

3 To RevisionEPage AddedPin Configurationand Functionssection,HandlingRatingtable,Fea tureDescriptionsection,DeviceFunctionalM odes,Applicationand Implementationsection,PowerSupplyRecomme ndationssection,Layoutsection,Deviceand DocumentationSupportsection,andMechanica l,Packaging,and (April2009)to RevisionDPage Addednew applicationto AddedRMNP ackageto UpdatedPin Addedadditonalgraphsto 2007 2015, OCTOBER2007 REVISEDFEBRUARY20155 Pin Configurationand FunctionsPin FunctionsPIN kV(1)Biasfor TMDS protectionLV_SUPPLY213 PWR2 kV(1)Biasfor CE/DDC/HOTPLUG levelshifters3, 5, 8, 11,14,6, 9, 10,GND,TMDS_GND25, 28, 31, 34,GNDNATMDSESDand parasiticGNDreturn(2)14, 1736 TMDS_D2+4, 3518IO8 kV(3) (4)TMDS_D2 6, 3319IO8 kV(3) (4)TMDS_D1+7, 3215IO8 kV(3) (4)TMDS_D1 9, 3016IO8 kV(3) (4)TMDS_D0+10, 298IO8 kV(3) (4)TMDS_D0 12, 277IO8 kV(3) (4)TMDS_CK+13, 265IO8 kV(3) (4)TMDS_CK 15, 244IO8 kV(3) (4)CE_REMOTE_IN1620IO2 kV(1)LV_SUPPLY referencedlogiclevelinto ASICDDC_CLK_IN1721IO2 kV(1)LV_SUPPLY referencedlogiclevelinto ASICDDC_DAT_IN1822IO2 kV(1)LV_SUPPLY referencedlogiclevelinto ASICHOTPLUG_DET_IN1923IO2 kV(1)LV_SUPPLY referencedlogiclevelinto ASIC5 V_SUPPLY referencedlogiclevelout, plus (5)toHOTPLUG_DET_OUT2024IO8 kV(3)connector(1)Humanbodymodel(HBM)per MIL-STD-883,Method3015,CDISCHARGE= 100 pF, RDISCHARGE= k , 5V_SUPPLYand LV_SUPPLY withinrecommendedoperatingconditions,GND = 0 V, and ESD_BYP(pin 37) and HOTPLUG_DET_OUT(pin 20) eachbypassedwitha F ceramiccapacitorconnectedto GND.

4 (2)Thesepins shouldbe routeddirectlyto the associatedGNDpins on the hdmi connector,with single-pointgroundvias at the connector.(3)StandardIEC 61000-4-2,CDISCHARGE= 150 pF, RDISCHARGE= 330 , 5V_SUPPLYand LV_SUPPLY withinrecommendedoperatingconditions,GND = 0 V, and ESD_BYP(pin 37) and HOTPLUG_DET_OUT(pin 20) eachbypassedwith a F ceramiccapacitorconnectedto GND.(4)Thesetwo pins mustbe connectedtogetherinlineon the PCB.(5)This outputcan be connectedto an F ceramiccapacitor,resultingin an 2007 2015,TexasInstrumentsIncorporatedSubmitD ocumentationFeedback3 ProductFolderLinks:TPD12S520 TPD12S520 SLVS640F OCTOBER2007 Functions(continued)PIN V_SUPPLY referencedlogiclevelout, plus kV(3)connector5 V_SUPPLY referencedlogiclevelout, plus kV(3)connector5 V_SUPPLY referencedlogiclevelout, plus kV(3) pin mustbe connectedto a F ceramicESD_BYP3711IO2 kV(1) connection6 (1)overoperatingfree-airtemperaturerange (unlessotherwisenoted)MINMAXUNITV5V_SUPP LYS upplyvoltage voltageat any channelinput Temperature 4085 CTstgStoragetemperaturerange 65150 C(1)StressesbeyondthoselistedunderAbsolu teMaximumRatingsmay causepermanentdamageto the stressratingsonly,and functionaloperationof the deviceat theseor any otherconditionsbeyondthoseindicatedunder RecommendedOperatingConditionsis not absolute-maximum-ratedconditionsfor extendedperiodsmay (HBM)

5 ,per MIL-STD-SeePin Configuration883,Method3015,CDISCHARGE= 100 pF, 2000and FunctionsRDISCHARGE= k (1)V(ESD)ElectrostaticdischargeVSeePin ConfigurationIEC 61000-4-2 ContactDischarge(2) 8000and Functions(1)JEDEC documentJEP155statesthat 500-VHBM allowssafe manufacturingwith a than500-VHBMis possiblewith the necessaryprecautions.(2)JEDEC documentJEP157statesthat 250-VCDM allowssafe manufacturingwith a than250-VCDMis possiblewith the (unlessotherwisenoted)MINTYPMAXUNITTAO peratingfree-airtemperature 4085 2007 2015, OCTOBER2007 (1)DBTRMNUNIT38 PINS24 PINSR JC(top)Junction-to-case(top) C/W (1)For moreinformationabouttraditionaland new thermalmetrics,see theIC PackageThermalMetricsapplicationreport, (unlessotherwisenoted)PARAMETERTESTCONDI TIONSMINTYPMAXUNITI5 VOperatingsupplycurrent5V_SUPPLY= 5 V15 AILVB iassupplycurrentLV_SUPPLY= V12mAOFF-stateleakageIOFF current,level-shiftingLV_SUPPLY= 0 ANFETTMDS_D[2.]

6 0]+/ ,TMDS_CK+/ ,CurrentconductedfromCE_REMOTE_OUT,outpu tpins toIBACKDRIVE5V_SUPPLY< AV_SUPPLY rails whenDDC_DAT_OUT,powereddownDDC_CLK_OUT,H OTPLUG_DET_OUTV oltagedropacrossVONlevel-shiftingNFET whenLV_SUPPLY= V, VS= GND,IDS= 3 mA7595140mVONIF= 8 mA,Top diode1 VFDiodeforwardvoltageVTA= 25 C(1)Bottomdiode1 Positivetransients9 ChannelclampvoltageatVCLTA = 25 C(1)(2)V 8 kV = 1 A, TA= 25 C(3) 25 C(1) AILEAK currentCIN,5V_SUPPLY=5 V, Measuredat 1 MHz, V(1) CIN,5V_SUPPLY=5 V, Measuredat 1 MHz, V(1)(4)Mutualcapacitance5V_SUPPLY=0 V, Measuredat 1 MHz,CMUTUAL betweensignalpin V(1) V, Measuredat 100 KHz,CINcapacitance, V(1)to (1)This parameteris specifiedby designand verifiedby devicecharacterization(2)Human-BodyModel (HBM)per MIL-STD-883,Method3015,CDISCHARGE= 100 pF, RDISCHARGE= k (3)Thesemeasurementsperformedwith no externalcapacitoron ESD_BYP.

7 (4)Intrapairmatching,eachTMDS pair ( ,D+, D )Copyright 2007 2015,TexasInstrumentsIncorporatedSubmitD ocumentationFeedback5 ProductFolderLinks:TPD12S520 33 30 27 24 21 18 15 12 9 6 3 + + + + + +10 Gain (dB) Frequency (Hz) C004 (pF) Bias Voltage (V) C005 050100150200250300350400450500-50-35-20- 5102540557085 Current (nA) Temperature (SC) C007 10 0102030405060708090 15 0153045607590105120135150165180 Voltage (V) Time (nS) C001 90 80 70 60 50 40 30 20 10 010-150153045607590105120135150165180 Voltage (V) Time (nS) C002 TPD12S520 SLVS640F OCTOBER2007 TPD12S520 RMNIEC ClampingWaveforms+8kVFigure2. TPD12S520 RMNIEC ClampingWaveforms-8kVContactContactFigur e3. ILEAKvs. TemperatureVIN = Capacitancevs. VBIASF igure5. InsertionLossPerformanceAcrossFrequency6 SubmitDocumentationFeedbackCopyright 2007 2015,TexasInstrumentsIncorporatedProduct FolderLinks:TPD12S520 TMDS_D2+TMDS_GNDTMDS_D2 TMDS_D1+TMDS_GNDTMDS_D1 TMDS_D0+TMDS_GNDTMDS_D0 TMDS_CK+TMDS_GNDTMDS_CK 5V_SUPPLYDDC_DAT_OUTHOTPLUG_DET_OUTESD_B YPLV SupplyLV SupplyCE_REMOTE_INCE_REMOTE_OUTDDC_DAT_I NLV SupplyLV OCTOBER2007 REVISEDFEBRUARY20157 TPD12S520is a single-chipESDsolutionfor the manycasesthe coreICs, suchasthe scalarchipset,maynot haverobustESDcellsto thesecases,theTPD12S520providesthe desiredsystem-levelESDprotection,suchas the IEC61000-4-2(Level4) ESD,byabsorbingthe energyassociatedwith the ESDprotection,the TPD12S520addslittleor no additionalglitchin the high-speeddifferentialsignals(seeFigure7 and Figure8).

8 The high-speedTMDS linesadd only addition,the monolithicintegratedcircuittechnologyens uresthat thereis excellentmatchingbetweenthe two-signalpair of the a directadvantageoverdiscreteESDclampsolut ionswherevariationsbetweentwo differentESDclampsmay significantlydegradethe low-speedcontrollinesoffervoltage-levels hiftingto eliminatethe needfor an externalvoltagelevel-shifterIC. The controlline ESDclampsadd the 38-pinDBTpackageoffersaseamlesslayoutrou tingoptionto eliminatethe routingglitchfor the ( mm) addition,pin mappingfollowsthe sameorderas the hdmi connectorpin 24-pinRMNpackageoffersflow throughroutingusingonlytwo layersfor highlyintegrated,space-efficientfull 2007 2015,TexasInstrumentsIncorporatedSubmitD ocumentationFeedback7 ProductFolderLinks:TPD12S520 TPD12S520 SLVS640F OCTOBER2007 8-kVContactESDP rotectionon ExternalLinesIn manycases,the coreICs, suchas the scalarchipset,maynot haverobustESDcellsto thesecases,the TPD12S520providesthe desiredsystem-levelESDprotection,suchas theIEC61000-4-2(Level4)

9 ESD,by absorbingthe energyassociatedwith the HDMID riverTPD12S520providesa completeESDprotectionschemefor an excellentmatchingbetweenthe two-signalpairof a directadvantageoverdiscreteESDclampsolut ionswherevariationsbetweentwodifferentES Dclampsmaysignificantlydegradethe 38-pinDBTpackageoffersaseamlesslayoutrou tingoptionto eliminatethe routingglitchfor the and high-speedTMDS pins of the TPD12S520add only pF of capacitanceto the capacitancematchingof providesultralow dB point> 3 GHzprovidesenoughbandwidthto passall 38-pinDBTpackageoffersseamlesslayoutrout ingoptionto eliminatethe routingglitchfor the ( mm)matcheswith addition,pin mappingfollowsthesameorderas the hdmi connectorpin protectionand interfacedeviceisspecificallydesignedfor SpaceConstrainedApplicationsThe 24-pinRMNpackageoffersflow throughroutingusingonly two layersfor highlyintegrated,space-efficientfull the ControlLinesThe low-speedcontrollinesoffervoltage-levels hiftingto eliminatethe needfor an externalvoltagelevel-shifterIC.

10 The controlline ESDclampsadd the offeredon the connectorside activewiththe conditionsin bi-directionalvoltage-leveltranslatorspr ovidenon-invertinglevelshiftingfromeithe r5V (for SDA, SCL,HPD),or V (forCEC)on the connectorside to VLVon the pin has an ESDclampthat triggerswhenvoltagesare aboveVBRor belowthe lowerdiode'sVf. DuringESDevents,voltagesas highas 8-kV(contactESD)can be directedto groundvia the voltageson the protectedlinefall belowthesetriggerlevels(usuallywithin10' s of nano-seconds),thesepins revertto a 2007 2015,TexasInstrumentsIncorporatedProduct FolderLinks:TPD12S520 VLV5 V5 V27 kO 47 kOTPD12S52147 kO100 kO 10 kO 47 kO TMDS LINES TMDS LINESHDMI ReceiverTPD12S520 hdmi Connector1 kO UFCECDCLKDDATHPDCECDCLKDDATHPD5 OCTOBER2007 REVISEDFEBRUARY20158 Applicationand ImplementationNOTEI nformationin the followingapplicationssectionsis not partof the TI componentspecification,and TI doesnot warrantits accuracyor s customersareresponsiblefor determiningsuitabilityof componentsfor test theirdesignimplementationto ContactESDratingto the boardspaceneededto implementthe designedto protecta Figure6 for a eightTMDS datalines(D2+/-,D1+/-,D0+/-,CLK+/-)eachh avetwo pins on TPD12S520to connectto.