SN74CBTLV16212 - Texas Instruments

1 SCDS044I DECEMBER 1997 REVISED OCTOBER 20031 POST OFFICE BOX 655303 DALLAS, Texas 75265 DMember of the Texas InstrumentsWidebus FamilyD4- Switch Connection Between Two PortsDRail-to-Rail Switching on Data I/O PortsDIoff Supports Partial-Power-Down ModeOperationDBreak-Before-Make FeatureDLatch-Up Performance Exceeds 100 mA PerJESD 78, Class IIDESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A)description/ordering informationThe SN74 CBTLV16212 provides 24 bits ofhigh-speed bus switching or exchanging. The lowon-state resistance of the switch allowsconnections to be made with minimal device operates as a 24-bit bus switch or a12-bit bus exchanger, which provides dataexchanging between the four signal ports via thedata-select (S0, S1, S2) device is fully specified forpartial-power-down applications using Ioff.

2 The Iofffeature ensures that damaging current will notbackflow through the device when it is powereddown. The device has isolation during power SN74 CBTLV16212 is specified by thebreak-before-make feature to have no throughcurrent when switching between B INFORMATIONTAPACKAGE ORDERABLEPART NUMBERTOP-SIDEMARKINGSSOP DLTubeSN74 CBTLV16212 DLCBTLV16212 40 C to 85 CSSOP DLTape and reelSN74 CBTLV16212 DLRCBTLV16212 40 C to 85 CTSSOP DGGTape and reelSN74 CBTLV16212 GRCBTLV16212 TVSOP DGVTape and reelSN74 CBTLV16212 VRCN212 Package drawings, standard packing quantities, thermal data, symbolization, and PCB designguidelines are available at !"# $ %& ' # "$ (&)* %"# +"#', +&%#$ % ! # $('% %"# $ (' #-' #' !$ '."$ $# &!' #$$#" +" + /" " #0, +&%# ( %'$$ 1 + '$ # '%'$$" *0 %*&+'#'$# 1 "** (" "!))))

3 '#' $,Copyright 2003, Texas Instruments IncorporatedDGG, DGV, OR DL PACKAGE(TOP VIEW)12345678910111213141516171819202122 2324252627285655545352515049484746454443 4241403938373635343332313029S01A11A22A12 A23A13A2 GND4A14A25A15A26A16A27A17A2 VCC8A1 GND8A29A19A210A110A211A111A212A112A2S1S2 1B11B22B12B23B1 GND3B24B14B25B15B26B16B27B17B28B1 GND8B29B19B210B110B211B111B212B112B2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data is a trademark of Texas Instruments . SCDS044I DECEMBER 1997 REVISED OCTOBER 20032 POST OFFICE BOX 655303 DALLAS, Texas 75265 FUNCTION TABLEINPUTSINPUTS/OUTPUTSFUNCTIONS2S1S0A 1A2 FUNCTIONLLLZZD isconnectLLH B1ZA1 port = B1 portLHL B2ZA1 port = B2 portLHH ZB1A2 port = B1 portHLL ZB2A2 port = B2 portHLH ZZDisconnectHHL B1B2A1 port = B1 portA2 port = B2 portHHHB2B1A1 port = B2 portA2 port = B1 port SCDS044I DECEMBER 1997 REVISED OCTOBER 20033 POST OFFICE BOX 655303 DALLAS, Texas 75265logic diagram (positive logic)12B212B11B21B112A212A11A21A1S0S1S2 SWSWSWSWSWSWSWSW2327285453302915655 SCDS044I DECEMBER 1997 REVISED OCTOBER 20034 POST OFFICE BOX 655303 DALLAS, Texas 75265simplified schematic, each FET switchA(OE)Babsolute maximum ratings over operating free-air temperature range (unless otherwise noted)

4 Supply voltage range, VCC V to V.. Input voltage range, VI (see Note 1) V to V.. Continuous channel current 128 mA.. Input clamp current, IIK (VI < 0) 50 mA.. Package thermal impedance, JA (see Note 2): DGG package 64 C/W.. DGV package 48 C/W.. DL package 56 C/W.. Storage temperature range, Tstg 65 C to 150 C.. Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device : 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are The package thermal impedance is calculated in accordance with JESD operating conditions (see Note 3)MINMAXUNITVCCS upply control input voltageVCC = V to control input voltageVCC = V to V2 VVILLow-level control input voltageVCC = V to control input voltageVCC = V to free-air temperature 4085 CNOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation.

5 Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004. SCDS044I DECEMBER 1997 REVISED OCTOBER 20035 POST OFFICE BOX 655303 DALLAS, Texas 75265electrical characteristics over recommended operating free-air temperature range (unlessotherwise noted)PARAMETERTEST CONDITIONSMINTYP MAXUNITVIKVCC = 3 V,II = 18 mA = V,VI = VCC or GND 1 AIoffVCC = 0,VI or VO = 0 to V10 AICCVCC = V,IO = 0,VI = VCC or GND10 A ICC Control inputsVCC = V,One input at 3 V,Other inputs at VCC or GND300 ACiControl inputsVI = 3 V or 05pFCio(OFF)VO = 3 V or 0,S1, S2, and S3 = GND8pFVCC = V,VI = 0II = 64 mA58 VCC = V,TYP at VCC = VVI = 0II = 24 mA58ron TYP at VCC = VVI = V,II = 15 mA2740 ron VI = 0II = 64 mA57 VCC = 3 VVI = 0II = 24 mA57 VCC = 3 VVI = V,II = 15 mA1015 All typical values are at VCC = V (unless otherwise noted), TA = 25 C.

6 This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND. Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined bythe lower of the voltages of the two (A or B) characteristics over recommended operating free-air temperature range (unlessotherwise noted) (see Figure 1)PARAMETERFROM(INPUT)TO(OUTPUT)VCC = V VVCC = V VUNITPARAMETER(INPUT)(OUTPUT)MINMAXMINMA XUNITtpd A or BB or or or or The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, whendriven by an ideal voltage source (zero output impedance). SCDS044I DECEMBER 1997 REVISED OCTOBER 20036 POST OFFICE BOX 655303 DALLAS, Texas 75265 PARAMETER MEASUREMENT INFORMATIONVCC/2thtsuFrom OutputUnder TestCL(see Note A)LOAD CIRCUITS12 VCCOpenGNDRLRLData InputTiming InputVCC0 VVCC0 V0 VtwInputVOLTAGE WAVEFORMSSETUP AND HOLD TIMESVOLTAGE WAVEFORMSPROPAGATION DELAY TIMESINVERTING AND NONINVERTING OUTPUTSVOLTAGE WAVEFORMSPULSE DURATIONtPLHtPHLtPHLtPLHVOHVOHVOLVOLVCC0 VInputOutputWaveform 1S1 at 2 VCC(see Note B)OutputWaveform 2S1 at GND(see Note B)VOLVOHtPZLtPZHtPLZtPHZVCC0 VVOL + V VOH V 0 VVCCVOLTAGE WAVEFORMSENABLE AND DISABLE TIMESLOW- AND HIGH-LEVEL ENABLINGO utputOutputtPLH/tPHLtPLZ/tPZLtPHZ/tPZHOp en2 VCCGNDTESTS1 NOTES: A.

7 CL includes probe and jig Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output 2 is for an output with internal conditions such that the output is high except when disabled by the output All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 The outputs are measured one at a time with one transition per tPLZ and tPHZ are the same as tPZL and tPZH are the same as tPLH and tPHL are the same as All parameters and waveforms are not applicable to all V V V500 500 VV CL30 pF50 pFFigure 1. Load Circuit and Voltage WaveformsPACKAGE OPTION 1 PACKAGING INFORMATIONO rderable DeviceStatus(1)Package TypePackageDrawingPinsPackageQtyEco Plan(2)Lead finish/Ball material(6)MSL Peak Temp(3)Op Temp ( C)Device Marking(4/5)

8 Samples74 CBTLV16212 DLRG4 ACTIVESSOPDL561000 RoHS & GreenNIPDAUL evel-1-260C-UNLIM-40 to 85 CBTLV1621274 CBTLV16212 GRE4 ACTIVETSSOPDGG562000 RoHS & GreenNIPDAUL evel-1-260C-UNLIM-40 to 85 CBTLV1621274 CBTLV16212 GRG4 ACTIVETSSOPDGG562000 RoHS & GreenNIPDAUL evel-1-260C-UNLIM-40 to 85 CBTLV16212SN74 CBTLV16212 DLACTIVESSOPDL5620 RoHS & GreenNIPDAUL evel-1-260C-UNLIM-40 to 85 CBTLV16212SN74 CBTLV16212 DLRACTIVESSOPDL561000 RoHS & GreenNIPDAUL evel-1-260C-UNLIM-40 to 85 CBTLV16212SN74 CBTLV16212 GRACTIVETSSOPDGG562000 RoHS & GreenNIPDAUL evel-1-260C-UNLIM-40 to 85 CBTLV16212SN74 CBTLV16212 VRACTIVETVSOPDGV562000 RoHS & GreenNIPDAUL evel-1-260C-UNLIM-40 to 85CN212 (1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new : TI has announced that the device will be discontinued, and a lifetime-buy period is in : Not recommended for new designs.

9 Device is in production to support existing customers, but TI does not recommend using this part in a new : Device has been announced but is not in production. Samples may or may not be : TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS : TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold.

10 Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device. PACKAGE OPTION 2(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.