The TMS320F2837xD Architecture: Achieving a …

1 Technical Brief SPRT720 February 2016. The TMS320F2837xD architecture : Achieving a New Level of High Performance Kenneth W. C2000 Technical Staff ABSTRACT. With the utilization of advanced high-performance microcontroller architectures, sophisticated real-time control systems can be realized. By combining both analog and digital control peripherals into a single device, along with a dual-core design, these systems can be cost-effectively implemented. This document provides an introduction and general overview to the TMS320F2837xD device architectural features. Even though the topics presented in this document are based on the TMS320F2837xD dual-core device family, most all of the topics are fully applicable to the TMS320F2837xS and TMS320F2807x single-core device families.

2 Contents 1 Introduction .. 2. 2 The C28x Core Processor .. 3. 3 4. 4 Reset and Clocks .. 5. 5 Boot Modes .. 6. 6 Interrupt Structure .. 8. 7 General-Purpose Input/Output (GPIO) Structure .. 10. 8 Crossbars (X-BAR) .. 10. 9 Analog Subsystem .. 12. Analog-to-Digital Converter (ADC) .. 13. Comparator Subsystem (CMPSS) .. 14. Buffered Digital-to-Analog Converter (DAC) .. 15. 10 Control Peripherals .. 15. Enhanced Pulse Width Modulator (ePWM) Module .. 15. Enhanced Capture (eCAP) Module .. 18. Enhanced Quadrature Encoder Pulse (eQEP) Module .. 19. Sigma-Delta Filter Module (SDFM) .. 19. 11 Control Law Accelerator (CLA) .. 19. 12 Direct Memory Access (DMA) .. 20. 13 Inter-Processor Communications (IPC).

3 21. 14 Communications Peripherals .. 22. 15 Summary .. 23. List of Figures 1 F2837xD Functional Block Diagram .. 2. 2 Simplified Memory Map .. 4. 3 Emulation Boot Mode .. 7. 4 Stand-Alone Boot 8. 5 Peripheral Interrupt Expansion (PIE) Module .. 9. 6 General-Purpose Input/Output (GPIO) Pin Block Diagram .. 10. 7 Input X-BAR .. 11. C2000 is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. SPRT720 February 2016 The TMS320F2837xD architecture : Achieving a New Level of High 1. Submit Documentation Feedback Performance Copyright 2016, Texas Instruments Incorporated Introduction 8 Output and ePWM X-BARs .. 12. 9 Analog-to-Digital Converter (ADC) Block Diagram.

4 13. 10 Comparator Subsystem (CMPSS) Block Diagram .. 15. 11 Enhanced Pulse Width Modulator (ePWM) Module Block Diagram .. 16. 12 Enhanced Capture (eCAP) Module Block Diagram .. 18. 13 Enhanced Quadrature Encoder Pulse (eQEP) Module Block Diagram .. 19. 14 Control Law Accelerator (CLA) Block Diagram .. 20. 15 Direct Memory Access (DMA) Triggers, Sources, and Destinations .. 21. List of Tables 1 Device Matrix .. 23. 1 Introduction Many control systems utilize powerful high performance microcontrollers in order to meet real-time design requirements. In addition to the microcontroller, these systems require various analog components to sense signals for the feedback control loops, as well as for hardware protection.

5 Some advanced control systems may even require two microcontrollers: for example one can be used to track speed and position, while the other can be used to control torque and current loops. A system implementation such as this might be intelligently partitioned; however, communications between the two microcontrollers can dramatically increase the complexity of the system design. Ideally, combining the two microcontrollers with a common communication link between them, along with the necessary analog components into a single device would increase system performance and reliability, and at the same time simplify the board layout and reduce the overall system cost. To address these types of high performance applications, the C2000 family of microcontrollers from Texas Instruments developed a special class of dual-core devices.

6 User User Configurable Configurable Dual PSWD DCSM DCSM PSWD Dual Code OTP OTP Code Security 1K x 16 1K x 16 Security Module Module + +. Emulation FLASH FLASH Emulation Secure Memories Code 256K x 16 256K x 16 Code Secure Secure shown in Red Security Security Logic Logic (ECSL) PUMP (ECSL). OTP/Flash OTP/Flash Wrapper Wrapper MEMCPU1 MEMCPU2. RAM 1Kx16 Low-Power GPIO Mux Mode Control to CPU1 CPU2 to C28 CPU-1 RAM 1Kx16 C28 CPU-2 128x16 MSG RAM. 128x16 MSG RAM. FPU FPU. CPU1 to to CPU2. 128x16 MSG RAM VCU-II RAM 1Kx16 VCU-II 128x16 MSG RAM. TMU TMU Watchdog 1/2 INTOSC1. RAM 1Kx16. CPU1 Local Shared CPU2 Local Shared 6x 2Kx16 6x 2Kx16. LS0-LS5 RAMs Interprocessor LS0-LS5 RAMs Communication RAM 2Kx16 (IPC) RAM 2Kx16.

7 Module Main PLL INTOSC2. RAM 2Kx16 RAM 2Kx16. WD Timer WD Timer Data ROM NMI-WDT NMI-WDT Data ROM. (4Kx16) Global Shared (4Kx16) External Crystal or 16x 4Kx16 Oscillator CPU Timer 0 GS0-GS15 RAMs CPU Timer 0. CPU Timer 1 CPU Timer 1. A5:0 16-/12-bit ADC Secure-ROM 32Kx16. CPU Timer 2 CPU Timer 2. Secure-ROM 32Kx16 Aux PLL. A Secure Secure x4 CPU1 to CPU2 AUXCLKIN. B5:0 B Boot-ROM 32Kx16 ePIE 1Kx16 MSG RAM ePIE Boot-ROM 32Kx16. C Non Secure (up to 192 (up to 192 Non Secure ADC TRST. C5:2 Analog D Result interrupts) CPU2 to CPU1 interrupts). 1Kx16 MSG RAM TCK. Mux Config Regs Bus Bus D5:0 JTAG TDI. TMS. ADCIN14. Data Bus TDO. ADCIN15 Bridge Comparator DAC CPU1 Buses SubSystem (CMPSS) x3.

8 CPU2 Buses Data Bus Data Bus Data Bus Data Bus Data Bus Peripheral Frame 1 Data Bus Bridge Bridge Bridge Peripheral Frame 2 Bridge Bridge Bridge ePWM-1/../12 SCI- USB CAN- SPI- RAM. eCAP- I2C-A/B McBSP- eQEP-1/2/3 SDFM-1/2 A/B/C/D Ctrl / A/B A/B/C uPP EMIF1 EMIF2 GPIO. HRPWM-1/../8 1/../6 (16L FIFO) A/B. (CPU1 only) (16L FIFO) PHY (32-MBOX) (16L FIFO). EXTSYNCOUT. UPPAD[7:0]. EPWMxB. EPWMxA. SCITXDx CANTXx UPPACLK. SPISIMOx SPISOMIx EM1 CTLx EM2 CTLx SPICLKx UPPAWT. MCLKRx UPPAEN. MCLKXx EQEPxS. SPISTEx UPPAST. EXTSYNCIN. USBDM. SDx_Dy SDx_Cy EQEPxI. MDXx USBDP. MFSRx SCIRXDx MFSXx EM1Dx EM1Ax EM2Dx EM2Ax CANRXx GPIOn EQEPxB. ECAPx EQEPxA. TZ1-TZ6. MRXx SDAx SCLx GPIO MUX, Input X-BAR, Output X-BAR.

9 Figure 1. F2837xD Functional Block Diagram 2 The TMS320F2837xD architecture : Achieving a New Level of High SPRT720 February 2016. Performance Submit Documentation Feedback Copyright 2016, Texas Instruments Incorporated The C28x Core Processor The TMS320F2837xD microcontroller (MCU) family, referred to as the F2837xD in this document, is a dual-core MCU design based on the TI 32-bit C28x CPU architecture . Each core is identical with access to its own local RAM and Flash memory, as well as globally shared RAM memory. Sharing information between the two CPU cores is accomplished with an Inter-Processor Communications (IPC) module. Additionally, each core shares access to a common set of highly integrated analog and control peripherals, providing a complete solution for demanding real-time high-performance signal processing applications, such as digital power, industrial drives, inverters, and motor control.

10 In addition to the high-performance CPUs, each core has a Control Law Accelerator (CLA), which is an independent 32-bit floating-point processor designed to execute math intensive calculations. The CLA runs concurrently and at the same speed of the main CPU, thereby effectively doubling the computational performance of each core. With each CPU running at 200 MHz, the CLAs can then effectively boost the total performance of the device to 800 MIPS. In-depth details about this device can be found in the technical documentation. Although this document is based on the F2837xD dual-core device family, most all topics are fully applicable to the F2837xS single- core device family and the F2807x device family which has been designed for cost-sensitive applications.