TI's new C66x Fixed- and Floating-Point DSP Core …

1 introduction Texas Instruments (TI s) new TMS320C66x digital signal processor (DSP) core brings significant performance enhancement to the award-winning C64x+ instruction set archi-tecture (ISA) and incorporates support for float-ing-point computations in the same processing core. For the first time, Floating-Point pro-cessing is available in a processor operating at speeds that are traditionally available only for Fixed- point processing.

2 The C66x DSP s ISA supports both single and double precision Floating-Point operations and is fully IEEE 754 compliant. The combination creates a DSP like no other, bringing the benefits of floating point to a high-speed embedded architecture without sacrificing fixed- or Floating-Point functionality. Unlike many embedded processors that provide Floating-Point companion units, TI s new C66x DSP core embeds the Floating-Point instruction set directly into the C64x+ Fixed- point instruction set.

3 On the C66x CPU customers can choose to execute fixed or floating point on an instruction by instruction basis as the fixed- and floating point capability is fully integrated. The question of whether to use a Fixed- point DSP, or a float-ing-point DSP is no longer a design challenge because the C66x DSP incorporates s new TMS320C66x fixed- and Floating-Point DSP core conquers the Need for Speed Integrating fixed- and Floating-Point capability in the same DSP core enables a fundamental change in the way algorithms for embedded systems are developed and deployed.

4 This may sound overstated, but it is true. The amount of effort that has been spent on implementing algorithms in fixed point digital systems is enormous. The need for speed mandated the effort because fast Floating-Point DSPs simply weren t available until now. Algorithms developed with Floating-Point tools like Matlab can be ported simply and easily to the DSP without a laborious conversion to fixed point. With TI s new C66x DSP Floating-Point computa-tion capabilities, most of this effort is no longer necessary.

5 A review of the binary representations of numbers All digital processors, including TI s DSPs, represent numbers in binary with a series of bits (0 s and 1 s). The accuracy with which we can represent numbers is dependent on both the number of bits used and also on the format of the representation. Fixed- point systems use the bits to represent a fixed range of values, either integers or with a fixed number of integer and fractional bits. The dynamic range of values is therefore quite limited and values outside of the set range must be saturated to the endpoints.

6 Fixed- point processors usually quote their 16-bit performance in terms of the number of such multiplies per second. To take full advantage of the processing capability ( to get the full entitlement of the quoted performance) algorithms developed for these processors have to operate on a set of data that stays within the pre-determined range. Data sets that are unpre-dictable or subject to wide variation do not perform well in Fixed- point implementations. Floating-Point representations provide more dynamic range by representing numbers in scientific notation, using a mantissa (or significand) and an exponent.

7 The C66x core imple-ments single precision Floating-Point operations where numbers are represented in 32 bits as: ( 1)5 M 2(N 127). where S is the sign bit, M is the mantissa or significand, and N is the exponent. S is one bit, N is represented in 8 bits and M is represented with 23 bits. In this way numbers in the range 2 127 2128 can be represented with 24 bits of precision in the significand. By contrast, a Fixed- point algorithm with 16 bits can only represent a range of 216 values (the numbers 0 65535) so there is much less dynamic range inherent in the numeri-cal representation.

8 Floating-Point representation is therefore preferred when the data sets, or the algorithms working on the data sets, are unpredictable or have wide variation in dynamic Arnon Friedmann Strategic marketing directorW H I T E P A P E RTI s new C66x fixed- and Floating-Point DSP core conquers the Need for Speed November 2010 2 Texas Instrumentsrange. The other important point is that the significand always has a 1 as its first digit so the values always retain 24 bits of New C66x DSP Core Figure 1 shows TI s C64x+ DSP, the predecessor to the new C66x DSP.

9 The core is composed of two symmetrical sides (A & B) each with four functional units. The .M unit contains the multipliers and there are four, sixteen bit multipliers in each of the .M + DSPTCI6487 multiplier unit contains 4. 16b multipliers (per side)16 fixed multipliescycle (per side)4 floating multiplies per cycle (per side)ABDR egisterfileLSMDR egisterfileLSMC66x C64x+16x16 MPY16x16 MPY16x16 MPY16x16 MPYF ixed16x16 MPY16x16 MPY16x16 MPY16x16 MPYF loat16x16 MPY16x16 MPY16x16 MPY16x16 MPYF loat16x16 MPY16x16 MPY16x16 MPY16x16 MPYF loatAddersAddersC64x+ DSPTCI6487 multiplier unit contains 4.

10 16b multipliers (per side)16 fixed multipliescycle (per side)4 floating multiplies per cycle (per side)ABDR egisterfileLSMDR egisterfileLSMC66x C64x+16x16 MPY16x16 MPY16x16 MPY16x16 MPYF ixed16x16 MPY16x16 MPY16x16 MPY16x16 MPYF loat16x16 MPY16x16 MPY16x16 MPY16x16 MPYF loat16x16 MPY16x16 MPY16x16 MPY16x16 MPYF loatAddersAddersFig. 1 TI s C64x+ DSPFig. 2 TI s new C66x DSP coreHow TI innovation integrated fixed- and Floating-Point in a single core Figure 2 shows TI s new C66x core with the same basic A & B structure of the C64x+ core.