TMS320C6652/54 Fixed and Floating-Point Digital …

1 Product Sample & Technical Tools & Support &. Folder Buy Documents Software Community TMS320C6652, TMS320C6654. SPRS841D MARCH 2012 REVISED JUNE 2016. TMS320C6652 and TMS320C6654 Fixed and Floating-Point Digital Signal Processor 1 Device Overview 1. Features One TMS320C66x DSP Core Subsystem 32-Bit DDR3 Interface (CorePac) DDR3-1066. C66x Fixed - and Floating-Point CPU Core: Up 8GB of Addressable Memory Space to 850 MHz for C6654 and 600 MHz for C6652 16-Bit EMIF. Multicore Shared Memory Controller (MSMC) Universal Parallel Port Memory Protection Unit for DDR3_EMIF Two Channels of 8 Bits or 16 Bits Each Multicore Navigator Supports SDR and DDR Transfers 8192 Multipurpose Hardware Queues with Two UART Interfaces Queue Manager Two Multichannel Buffered Serial Ports Packet-Based DMA for Zero-Overhead (McBSPs).

2 Transfers I2C Interface Peripherals 32 GPIO Pins PCIe Gen2 (C6654 Only) SPI Interface Single Port Supporting 1 or 2 Lanes Semaphore Module Supports up to 5 GBaud Per Lane Eight 64-Bit Timers Gigabit Ethernet (GbE) Subsystem (C6654 Two On-Chip PLLs Only). Commercial Temperature: One SGMII Port 0 C to 85 C. Supports 10-, 100-, and 1000-Mbps Extended Temperature: Operation 40 C to 100 C. Applications Power Protection Systems Medical Imaging Avionics and Defense Other Embedded Systems Currency Inspection and Machine Vision Industrial Transportation Systems Description The C6654 and C6652 are high performance Fixed - and Floating-Point DSPs that are based on TI's KeyStone multicore architecture.

3 Incorporating the new and innovative C66x DSP core, this device can run at a core speed of up to 850 MHz for C6654 and 600 MHz for C6652. For developers of a broad range of applications, both C6654 and C6652 DSPs enable a platform that is power-efficient and easy to use. In addition, the C6654 and C6652 DSPs are fully backward compatible with all existing C6000 family of Fixed - and Floating-Point DSPs. TI's KeyStone architecture provides a programmable platform integrating various subsystems (C66x cores, memory subsystem, peripherals, and accelerators) and uses several innovative components and techniques to maximize intradevice and interdevice communication that lets the various DSP resources operate efficiently and seamlessly.

4 Central to this architecture are key components such as Multicore Navigator that allows for efficient data management between the various device components. The TeraNet is a nonblocking switch fabric enabling fast and contention-free internal data movement. The multicore shared memory controller allows access to shared and external memory directly without drawing from switch fabric capacity. 1. An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers.

5 PRODUCTION DATA. TMS320C6652, TMS320C6654. SPRS841D MARCH 2012 REVISED JUNE 2016 For Fixed -point use, the C66x core has 4 the multiply accumulate (MAC) capability of C64x+ cores. In addition, the C66x core integrates Floating-Point capability and the per-core raw computational performance is an industry-leading GMACS per core and GFLOPS per core (@850 MHz frequency). The C66x core can execute 8 single precision Floating-Point MAC operations per cycle and can perform double- and mixed-precision operations and is IEEE 754 compliant. The C66x core incorporates 90 new instructions (compared to the C64x+ core) targeted for Floating-Point and vector math oriented processing.

6 These enhancements yield sizeable performance improvements in popular DSP. kernels used in signal processing, mathematical, and image acquisition functions. The C66x core is backward code-compatible with TI's previous generation C6000 Fixed - and Floating-Point DSP cores, ensuring software portability and shortened software development cycles for applications migrating to faster hardware. The C6654 and C6652 DSPs integrate a large amount of on-chip memory. In addition to 32KB of L1. program and data cache, 1024KB of dedicated memory can be configured as mapped RAM or cache.

7 All L2 memories incorporate error detection and error correction. For fast access to external memory, this device includes a 32-bit DDR-3 external memory interface (EMIF) running at a rate of 1066 MHz and has ECC DRAM support. This family supports a number of high-speed standard interfaces, PCI Express Gen2, and Gigabit Ethernet (PCIe and Gigabit Ethernet are not supported on the C6652). This family of DSPs also includes I2C, UART, Multichannel Buffered Serial Port (McBSP), Universal Parallel Port (uPP), and a 16-bit asynchronous EMIF, along with general-purpose CMOS IO.

8 The C6654 and C6652 devices have a complete set of development tools, which includes: an enhanced C. compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution. TI's KeyStone Multicore Architecture provides a high performance structure for integrating RISC and DSP. cores with application-specific coprocessors and I/O. The KeyStone architecture is the first of its kind that provides adequate internal bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O.

9 This internal bandwidth is achieved with four main hardware elements: Multicore Navigator, TeraNet, and Multicore Shared Memory Controller. Multicore Navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity of the TeraNet switched central resource to move packets. The Multicore Shared Memory Controller lets processing cores access shared memory directly without drawing from the capacity of TeraNet, so packet movement cannot be blocked by memory access.

10 Device Information (1). PART NUMBER PACKAGE BODY SIZE. GZH (625) 21 mm 21 mm TMS320C6652. CZH (625) 21 mm 21 mm GZH (625) 21 mm 21 mm TMS320C6654. CZH (625) 21 mm 21 mm (1) For more information, see Section 11, Mechanical Packaging and Orderable Information. 2 Device Overview Copyright 2012 2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C6652 TMS320C6654. TMS320C6652, TMS320C6654. SPRS841D MARCH 2012 REVISED JUNE 2016. Functional Block Diagram Figure 1-1 shows the functional block diagrams of the device. C6654. Memory Subsystem 32-Bit DDR3 EMIF MSMC.