TMS320C6746™ Fixed- and Floating-Point DSP

1 ProductFolderOrderNowTechnicalDocumentsT ools &SoftwareSupport &CommunityAn IMPORTANTNOTICEat the end of this datasheetaddressesavailability,warranty, changes,use in safety-criticalapplications,intellectual propertymattersand NOVEMBER2009 REVISEDJANUARY2017 TMS320C6746 Fixed- and floating -PointDSP1 375-and 456-MHzC674xFixed-and floating -PointVLIWDSP C674xInstructionSet Features Supersetof the C67x+and C64x+ISAs Up to 3648 MIPSand 2746 MFLOPS Byte-Addressable(8-, 16-, 32-, and 64-BitData) 8-BitOverflowProtection Bit-FieldExtract,Set, Clear Normalization,Saturation,Bit-Counting Compact16-BitInstructions C674xTwo-LevelCacheMemoryArchitecture 32 KBof L1P ProgramRAM/Cache 32 KBof L1D DataRAM/Cache 256 KBof L2 UnifiedMappedRAM/Cache FlexibleRAM/CachePartition(L1 and L2) EnhancedDirectMemoryAccessController3(ED MA3).

2 2 ChannelControllers 3 TransferControllers 64 IndependentDMAC hannels 16 QuickDMAC hannels ProgrammableTransferBurstSize TMS320C674xFloating-PointVLIWDSPCore Load-StoreArchitectureWithNonalignedSupp ort 64 General-PurposeRegisters(32-Bit) Six ALU(32- and 40-Bit)FunctionalUnits Supports32-BitInteger,SP (IEEES inglePrecision/32-Bit)and DP (IEEED oublePrecision/64-Bit)FloatingPoint Supportsup to FourSP AdditionsPer Clock,FourDP AdditionsEveryTwo Clocks Supportsup to Two Floating-Point (SP or DP)ReciprocalApproximation(RCPxP)andSqua re-RootReciprocalApproximation(RSQRxP)Op erationsPer Cycle Two MultiplyFunctionalUnits: Mixed-PrecisionIEEEF loating-PointMultiplySupportedup to: 2 SP SP SP Per Clock 2 SP SP DP EveryTwo Clocks 2 SP DP DP EveryThreeClocks 2 DP DP DP EveryFourClocks Fixed- PointMultiplySupportsTwo 32 32-Bit Multiplies,Four16 16-BitMultiplies,orEight8 8-BitMultipliesper ClockCycle,and ComplexMultiples InstructionPackingReducesCodeSize All InstructionsConditional HardwareSupportfor ModuloLoopOperation ProtectedModeOperation ExceptionsSupportfor ErrorDetectionandProgramRedirection SoftwareSupport TI DSPBIOS ChipSupportLibraryand DSPL ibrary (Exceptfor USBandDDR2 Interfaces) Two ExternalMemoryInterfaces.

3 EMIFA NOR(8- or 16-Bit-WideData) NAND(8- or 16-Bit-WideData) 16-BitSDRAMWith128-MBAddressSpace DDR2/MobileDDRM emoryControllerWithoneof the Following: 16-BitDDR2 SDRAMWith256-MBAddressSpace 16-BitmDDRSDRAMWith256-MBAddressSpace ThreeConfigurable16550-TypeUARTM odules: WithModemControlSignals 16-ByteFIFO 16x or 13x OversamplingOption Two SerialPeripheralInterfaces(SPIs)EachWith MultipleChipSelects Two MultimediaCard(MMC)/SecureDigital(SD)Car dInterfacesWithSecureDataI/O (SDIO)Interfaces Two Masterand SlaveInter-IntegratedCircuits(I2C Bus ) One Host-PortInterface(HPI)With16-Bit-WideMu xedAddressand DataBus For HighBandwidth2 TMS320C6746 SPRS591F NOVEMBER2009.

4 TMS320C6746 DeviceOverviewCopyright 2009 2017,TexasInstrumentsIncorporated ProgrammableReal-TimeUnit Subsystem(PRUSS) Two IndependentProgrammableReal-TimeUnit(PRU )Cores 32-BitLoad-StoreRISCA rchitecture 4KB of InstructionRAMPer Core 512 Bytesof DataRAMPer Core PRUSScan be DisabledThroughSoftwaretoSavePower Register30 of EachPRUis ExportedFromthe Subsystemin Additionto the NormalR31 Outputof the PRUC ores. StandardPower-ManagementMechanism ClockGating EntireSubsystemUndera SinglePSCC lockGatingDomain DedicatedInterruptController DedicatedSwitchedCentralResource OTGPort WithIntegratedPHY(USB0) High-and Full-SpeedClient High-,Full-,and Low-SpeedHost End Point0 (Control) End Points1, 2, 3, and 4 (Control,Bulk,Interrupt,or ISOC)RX and TX One MultichannelAudioSerialPort (McASP): Two ClockZonesand 16 SerialDataPins SupportsTDM,I2S, and SimilarFormats DIT-Capable FIFOB uffersfor Transmitand Receive Two MultichannelBufferedSerialPorts(McBSPs).

5 SupportsTDM,I2S, and SimilarFormats AC97 AudioCodecInterface TelecomInterfaces(ST-Bus,H100) 128-ChannelTDM FIFOB uffersfor Transmitand Receive 10/100 MbpsEthernetMAC(EMAC): MII Media-IndependentInterface RMIIR educedMedia-IndependentInterface ManagementDataI/O (MDIO)Module VideoPort Interface(VPIF): Two 8-BitSD ( ),Single16-Bitor SingleRaw(8-, 10-, and 12-Bit)VideoCaptureChannels Two 8-BitSD ( ),Single16-BitVideoDisplayChannels UniversalParallelPort (uPP): High-SpeedParallelInterfaceto FPGA sandDataConverters DataWidthon BothChannelsis 8- to 16-BitInclusive Single-DataRateor Dual-DataRateTransfers SupportsMultipleInterfacesWithSTART,ENAB LE,and WAITC ontrols Real-TimeClock(RTC)With32-kHzOscillatora ndSeparatePowerRail Three64-BitGeneral-PurposeTimers(EachCon figurableas Two 32-BitTimers) One 64-BitGeneral-Purposeor WatchdogTimer(Configurableas Two 32-BitGeneral-PurposeTimers) Two EnhancedHigh-ResolutionPulseWidthModulat ors(eHRPWMs).

6 Dedicated16-BitTime-BaseCounterWithPerio dand FrequencyControl 6 Single-EdgeOutputs,6 Dual-EdgeSymmetricOutputs,or 3 Dual-EdgeAsymmetricOutputs Dead-BandGeneration PWMC hoppingby High-FrequencyCarrier Trip ZoneInput Three32-BitEnhancedCapture(eCAP)Modules: Configurableas 3 CaptureInputsor 3 AuxiliaryPulseWidthModulator(APWM)Output s Single-ShotCaptureof up to FourEventTimestamps Packages: 361-BallPb-FreePlasticBall Grid Array(PBGA)[ZCES uffix], Pitch 361-BallPb-FreePBGA[ZWTS uffix], Pitch Commercial,Extended,or NOVEMBER2009 REVISEDJANUARY2017 SubmitDocumentationFeedbackProductFolder Links:TMS320C6746 DeviceOverviewCopyright 2009 2017, CurrencyInspection BiometricIdentification MachineVision(Low-End) TMS320C6746fixed-and floating -pointDSPis a low-powerapplicationsprocessorbasedon a the TMS320C6000 platformof deviceenablesoriginal-equipmentmanufactu rers(OEMs)and original-designmanufacturers(ODMs)to quicklybringto marketdeviceswith robustoperatingsystems,rich userinterfaces,and highprocessorperformancethroughthe maximumflexibilityof a fully integrated, deviceDSPcoreusesa level1 programcache(L1P)is a32-KBdirectmappedcache,and the level1 datacache(L1D)is a 32-KB2-way, level2 programcache(L2P)

7 Consistsof a 256-KBmemoryspacethat is sharedbetweenprogramand memorycan be configuredas mappedmemory,cache,or combinationsof the DSPL2 is accessibleby otherhostsin the peripheralset includes:a 10/100 MbpsEthernetmediaaccesscontroller(EMAC)w ith a managementdatainput/output(MDIO)module;o ne ;two I2C Bus interfaces;one multichannelaudioserialport (McASP)with16 serializersand FIFO buffers;two multichannelbufferedserialports(McBSPs)w ith FIFO buffers;two serialperipheralinterfaces(SPIs)with multiplechip selects;four 64-bitgeneral-purposetimerseachconfigura ble(oneconfigurableas a watchdog);a configurable16-bithost-port interface(HPI);up to 9 banksof general-purposeinput/output(GPIO)pins,wi th eachbankcontaining16 pinswithprogrammableinterruptand eventgenerationmodes,multiplexedwithothe rperipherals;threeUART interfaces(eachwith RTSand CTS);two enhancedhigh-resolutionpulsewidthmodulat or(eHRPWM)peripherals;three32-bitenhance dcapture(eCAP)moduleperipheralswhichcanb econfiguredas 3 captureinputsor 3 APWM outputs;two externalmemoryinterfaces:an asynchronousandSDRAM externalmemoryinterface(EMIFA)for slowermemoriesor peripherals.

8 And a higherspeedDDR2 EMAC providesan efficientinterfacebetweenthe deviceand a EMAC supportsboth10 Base-Tand 100 Base-TX,or 10 Mbpsand 100 Mbpsin eitherhalf-or ,anMDIO interfaceis availablefor EMAC supportsbothMII and (uPP)providesa high-speedinterfaceto manytypesof dataconverters,FPGAs,or uPPsupportsprogrammabledatawidthsbetween 8- to and double-datarate transfersare supportedas well as START,ENABLE,and WAIT signalsto providecontrolfor a varietyof videoport interface(VPIF)providesa flexiblevideoI/O rich peripheralset providesthe abilityto controlexternalperipheraldevicesand detailson eachperipheral,see the relatedsectionsin this documentand devicehas a completeset of developmenttoolsfor the compilers,a DSPassemblyoptimizerto simplifyprogrammingand scheduling,and a Windows debuggerinterfaceforvisibilityinto sourcecodeexecution.

9 (1)For moreinformationon thesedevices,see (1)PARTNUMBERPACKAGEBODYSIZETMS320C6746 ZCENFBGA(361)13,00mm x 13,00mmTMS320C6746 ZWTNFBGA(361)16,00mm x 16,00mmSwitched Central Resource (SCR)BOOT ROM256KB L2 RAM32 KBL1 RAM32 KBL1 PgmAETC674x DSP CPUDSP SubsystemJTAG InterfaceSystem ControlInputClock(s)Power/SleepControlle rPinMultiplexingPLL/ClockGeneratorw/OSCG eneral-PurposeTimer (x3)Serial InterfacesAudio PortsMcASPw/FIFODMAP eripheralsExternal Memory InterfacesConnectivityEDMA3(x2)Control TimersePWM(x2)eCAP(x3)EMIFA(8b/16B)NAND/ Flash16b SDRAMDDR2/MDDRC ontrollerRTC/32-kHzOSCI C(x2)2 SPI(x2)UART(x3)McBSP(x2)VideoVPIFP arallel PortuPPEMAC10/100(MII/RMII) CtlrPHYHPIMMC/SD(8b)(x2)Customizable InterfacePRU SubsystemMemoryProtection4 TMS320C6746 SPRS591F NOVEMBER2009 :TMS320C6746 DeviceOverviewCopyright 2009 2017, showsthe functionalblockdiagramof the NOVEMBER2009 REVISEDJANUARY2017 SubmitDocumentationFeedbackProductFolder Links:TMS320C6746 Tableof ContentsCopyright 2009 2017,TexasInstrumentsIncorporatedTableof Contents1 (UnlessOtherwiseNoted).

10 RecommendedPower-OnHours(POH). SupplyVoltageand OperatingJunctionTemperature(UnlessOther wiseNoted)..756 PeripheralInformationand SleepController(PSC).. (EDMA3).. (EMIFA).. SD / SDIO(MMCSD0,MMCSD1).. (McASP).. (McBSP).. (SPI0,SPI1).. (I2C).. (UART).. OTGC ontroller(USB0)[ ].. (EMAC).. (MDIO).. (UHPI).. (uPP).. Interface(VPIF).. (eCAP) (eHRPWM).. (RTC).. (GPIO).. Subsystem(PRUSS).. Deviceand MechanicalPackagingand NOVEMBER2009 :TMS320C6746 RevisionHistoryCopyright 2009 2017,TexasInstrumentsIncorporated2 RevisionHistoryNOTE:Pagenumbersfor previousrevisionsmay differfrompagenumbersin the , 2014to January31, 2017 Page RemovedinternalpullupdesignationfromRESE Tin Addedfootnoteto CLKOUTD escriptionin NOVEMBER2009 REVISEDJANUARY2017 SubmitDocumentationFeedbackProductFolder Links.