TMS320C674x DSP CPU and Instruction Set User's Guide

1 TMS320C674xDSPCPUandInstructionSetRefere nceGuideLiteratureNumber:SPRUFE8 BJuly20102 SPRUFE8B July2010 Copyright 2010, (CPU).. ,Load, (AMR).. (CSR).. (GFPGFR).. (ICR).. (IER).. (IFR).. (IRP).. (ISR).. (ISTP).. (NMI)ReturnPointerRegister(NRP).. (PCE1).. (DIER).. (DNUM).. (ECR).. (EFR).. A SideRegister(GPLYA).. B SideRegister(GPLYB).. (IERR).. (ILC).. (ITSR).. (NTSR).. (REP).. (RILC).. (SSR)..543 SPRUFE8B July2010 ContentsCopyright 2010, (TSCLandTSCH).. (TSR).. (FADCR).. (FAUCR).. (FMCR).. (1 Xand2X).. (40-Bit) July2010 Copyright 2010, (DP) a (IST).. (polling).. July2010 ContentsCopyright 2010, (EXCEP) (IERR).. (SPLOOP) (LBC).. (ILC).. (RILC).. (TSR),InterruptTaskStateRegister(ITSR),a ndNMI/ExceptionTaskStateRegister(NTSR).

2 ,SPLOOPD, ,Kernel, (D) July2010 Copyright 2010, (R) (D/W) , , July2010 ContentsCopyright 2010, ,.L, July2010 Copyright 2010, a (AMR).. (CSR).. (CSR).. (GFPGFR).. (ICR).. (IER).. (IFR).. (IRP).. (ISR).. (ISTP).. (NRP).. (PCE1).. (DIER).. (DNUM).. (EFR).. (GPLYA).. (GPLYB).. (IERR).. (ILC).. (ITSR).. (NTSR).. (RILC).. (SSR).. LowHalf(TSCL).. HighHalf(TSCH).. (TSR).. (FADCR).. (FAUCR).. (FMCR).. July2010 ListofFiguresCopyright 2010, (EXCEP) ,Kernel, () July2010 Copyright 2010, or2 or2 or2 or2 Sources, or2 Sources, or2 or2 ,ImmediatewithImpliedNOP5 July2010 ListofFiguresCopyright 2010, or2 Sources, , , July2010 Copyright 2010, (23).

3 (AMR) (CSR) (GFPGFR) (ICR) (IER) (IFR) (ISR) (ISTP) (DIER) (EFR) (IERR) (ITSR) (NTSR) (TSR) (FADCR) (FAUCR) (FMCR) ,OperandSize,FunctionalUnits,andOpfields forExampleInstruction(ADD).. July2010 ListofTablesCopyright 2010, (U) (U) Instruction (15-BitOffset).. (U) (U) Instruction (15-BitOffset).. July2010 Copyright 2010, Taken(EXC= 0).. ,C64x,C64x+,C67x,C67x+, ,.L, July2010 ListofTablesCopyright 2010,TexasInstrumentsIncorporated16 ListofTablesSPRUFE8B July2010 Copyright 2010,TexasInstrumentsIncorporatedPreface SPRUFE8B July2010 ReadThisFirstAboutThisManualTheTMS320C67 4x DSPis thenewgenerationfloating-pointDSPthatcom binestheTMS320C67x+ DSPandtheTMS320C64x+ ,pipeline,instructionset,andinterruptsof theC674x ,thefollowingnumberis 40hexadecimal(decimal64).

4 Entertheliteraturenumberin ,relatedperipherals,andothertechnicalcol lateral,is availablein theC6000 TMS320C674 (DSPs) (DSP) a discussionontheinternaldirectmemoryacces s(IDMA)controller,theinterruptcontroller ,thepower-downcontroller,memoryprotectio n,bandwidthmanagement, TMS320C674xDSPC acheUser' theTMS320C674xdigitalsignalprocessor(DSP )canbeefficientlyusedin ,howtouseDMAtoreducememorylatencies, theC674xDSPis organizedin a two-levelhierarchyconsistingofa dedicatedprogramcache(L1P)andadedicatedd atacache(L1D) thedatarequestedbytheCPUis notcontainedincache,it is fetchedfromthenextlowermemorylevel, ,TMS320C67x+,TMS320C64x+,C674x,TMS320C67 x+,TMS320C64x+,XDS510, a July2010 ReadThisFirstCopyright 2010,TexasInstrumentsIncorporated18 ReadThisFirstSPRUFE8B July2010 Copyright 2010,TexasInstrumentsIncorporatedChapter 1 SPRUFE8B July2010 IntroductionCopyright 2010, DSPis thenewgenerationfloating-pointDSPthatcom binestheTMS320C67x+ DSPandtheTMS320C64x+ megamoduleis thenameusedtodesignatetheCPUtogetherwith thehardwareprovidingmemory,bandwidthmana gement,interrupt,memoryprotection, ,pipeline,instructionset.

5 Notdescribedin thisdocumentsinceit is fullycoveredin theTMS320C674xDSPM egamoduleReferenceGuide(SPRUFK5). : Twomultipliers SixALUsTheC6000generationhasa completesetofoptimizeddevelopmenttools,i ncludinganefficientC compiler,anassemblyoptimizerforsimplifie dassembly-languageprogrammingandscheduli ng,andaWindows hardwareemulationboard,compatiblewiththe TIXDS510 andXDS560 emulatorinterface,is , : AdvancedVLIWCPU witheightfunctionalunits,includingtwomul tipliersandsixarithmeticunits Executesuptoeightinstructionspercyclefor uptotentimestheperformanceoftypicalDSPs AllowsdesignerstodevelophighlyeffectiveR ISC-likecodeforfastdevelopmenttime Instructionpacking Givescodesizeequivalenceforeightinstruct ionsexecutedseriallyorin parallel Reducescodesize,programfetches.

6 Andpowerconsumption Conditionalexecutionofmostinstructions Reducescostlybranching Increasesparallelismforhighersustainedpe rformance Efficientcodeexecutiononindependentfunct ionalunits Industry'smostefficientC compileronDSPbenchmarksuite Industry'sfirstassemblyoptimizerforfastd evelopmentandimprovedparallelization 8/16/32-bitdatasupport,providingefficien tmemorysupportfora varietyofapplications 40-bitarithmeticoptionsaddextraprecision forvocodersandothercomputationallyintens iveapplications Saturationandnormalizationprovidesupport forkeyarithmeticoperations Fieldmanipulationandinstructionextract,s et,clear,andbitcountingsupportcommonoper ationfoundin July2010 Copyright 2010, : Eachmultipliercanperformtwo16 16-bitorfour8 8 bitmultiplieseveryclockcycle.

7 Quad8-bitanddual16-bitinstructionsetexte nsionswithdataflowsupport Supportfornon-aligned32-bit(word)and64-b it(doubleword)memoryaccesses Specialcommunication-specificinstruction shavebeenaddedtoaddresscommonoperationsi nerror-correctingcodes. Bitcountandrotatehardwareextendssupportf orbit-levelalgorithms. Compactinstructions:Commoninstructions(A ND,ADD,LD,MPY)have16-bitversionstoreduce codesize. Protectedmodeoperation:A two-levelsystemofprivilegedprogramexecut iontosupporthighercapabilityoperatingsys temsandsystemfeaturessuchasmemoryprotect ion. Exceptionssupportforerrordetectionandpro gramredirectiontoproviderobustcodeexecut ion Hardwaresupportformoduloloopoperationtor educecodesize Eachmultipliercanperform32 32bitmultiplies Additionalinstructionstosupportcomplexmu ltipliesallowinguptoeight16-bitmultiply/ : Hardwaresupportforsingle-precision(32-bi t)anddouble-precision(64-bit)IEEE floating-pointoperations.

8 Executepacketscanspanfetchpackets. Registerfilesizeis increasedto64registers(32in eachdatapath). Floating-pointadditionandsubtractioncapa bilityin Mixed-precisionmultiplyinstructions. 32 traditionalVLIW architectureconsistsofmultipleexecutionu nitsrunningin parallel,performingmultipleinstructionsd uringa thekeytoextremelyhighperformance, a highlydeterministicarchitecture,havingfe wrestrictionsonhoworwheninstructionsaref etched,executed, is thisarchitecturalflexibilitythatis 'sadvancedfeaturesinclude: Instructionpacking:reducedcodesize Allinstructionscanoperateconditionally:f lexibilityofcode Variable-widthinstructions:flexibilityof datatypes July2010 IntroductionCopyright 2010.

9 D1 Register File AData Path .L2 Register File BData Path BInstruction Decode16/32-Bit Instruction DispatchSPLOOP BufferInstruction FetchIDMAP rogram Memory Controller (PMC)Data MemoryController(DMC)Interrupt& ExceptionControllerPowerControlUnifiedMe moryController(UMC)ExternalMemoryControl ler(EMC)L2 Cache/SRAML1P Cache/SRAML1D ,which,onsomedevices,canbeusedasa directmemoryaccess(DMA)controller,power- downlogic,andexternalmemoryinterface(EMI F)usuallycomewiththeCPU, July2010 Copyright 2010, (CPU)TheC674xCPU,in Figure1-1, contains: Programfetchunit 16/32bitinstructiondispatchunit,advanced instructionpacking Instructiondecodeunit Twodatapaths,eachwithfourfunctionalunits 6432-bitregisters Controlregisters Controllogic Test,emulation,andinterruptlogic InternalDMA(IDMA)fortransfersbetweeninte rnalmemoriesTheprogramfetch,instructiond ispatch, eachofthetwodatapaths(AandB),eachofwhich containsfourfunctionalunits(.)

10 L,.S,.M, ) moredetailin Chapter2. A ,dispatched,decoded,andexecutedin thedatapath, 32-bit, (on-chip)memoryis used,thesespacesareunifiedonmostdevicest oa singlememoryspaceviatheexternalmemoryint erface(EMIF).TheDSPhasa 256-bitread-onlyporttoaccessinternalprog rammemoryandtwo256-bitports(readandwrite ) ,refertotheTMS320C674x/OMAP-L1xProcessor PeripheralsOverviewReferenceGuide(SPRUFK 9) July2010 IntroductionCopyright 2010,TexasInstrumentsIncorporated24 IntroductionSPRUFE8B July2010 Copyright 2010,TexasInstrumentsIncorporatedChapter 2 SPRUFE8B July2010 CPUDataPathsandControlThischapterfocuses ontheCPU, ,Load, July2010 CPUDataPathsandControlCopyright 2010, Figure2-1. Thesecomponentsconsistof: Twogeneral-purposeregisterfiles(AandB) Eightfunctionalunits(.