TMS320F2833x, 2823x Serial Communications Interface (SCI

1 TMS320x2833x,2823xSerialCommunicationsIn terface(SCI)ReferenceGuideLiteratureNumb er:SPRUFZ5 AAugust2008 RevisedJuly20092 SPRUFZ5A August2008 (SCICCR).. (SCICTL1).. (SCIHBAUD,SCILBAUD).. (SCICTL2).. (SCIRXST).. (SCIRXEMU,SCIRXBUF).. (SCIRXEMU).. (SCIRXBUF).. (SCITXBUF).. (SCIFFTX,SCIFFRX,SCIFFCT).. (SCIPRI).. August2008 (SCI) (SCICCR) (SCICTL1) (SCIHBAUD) (SCILBAUD) (SCICTL2) (SCIRXST) (SCIRXEMU) (SCIRXBUF) (SCITXBUF) (SCIFFTX)Register (SCIFFRX)Register (SCIFFCT)Register (SCIPRI) August2008 (SCICCR) (SCICTL1) (SCICTL2) (SCIRXST) (SCIRXBUF) (SCIFFRX) (SCIFFCT) August2008 RevisedJuly2009 ListofTables5 SubmitDocumentationFeedbackListofTables6 SPRUFZ5A August2008 RevisedJuly2009 SubmitDocumentationFeedbackPrefaceSPRUFZ 5A August2008 RevisedJuly2009 ReadThisFirstAboutThisManualThismanualde scribesthefeaturesandoperationoftheseria lcommunicationinterface(SCI)modulethatis availableontheTMS320x2833x, ,28xxxPeripheralReferenceGuide(SPRU566)f oralistofalldeviceswithamoduleofthesamet ype,todeterminethedifferencesbetweentype s, ,thefollowingnumberis40hexadecimal(decim al64):40h.

2 Registersinthisdocumentareshowninfigures anddescribedintables. ,itsbeginningandendingbitnumbersabove, SPRS439 TMS320F28335,TMS320F28334,TMS320F28332,T MS320F28235,TMS320F28234,TMS320F28232 DigitalSignalControllers(DSCs)DataManual containsthepinout,signaldescriptions,asw ellaselectricalandtimingspecificationsfo rtheF2833 TMS320F28335,F28334,F28332,TMS320F28235, F28234,F28232 DigitalSignalControllers(DSCs) 'sGuides SPRU430 TMS320C28xDSPCPUandInstructionSetReferen ceGuidedescribesthecentralprocessingunit (CPU)andtheassemblylanguageinstructionso ftheTMS320C28xfixed-pointdigitalsignalpr ocessors(DSPs). SPRU566 TMS320x28xx,28xxxPeripheralReferenceGuid edescribestheperipheralreferenceguidesof the28xdigitalsignalprocessors(DSPs).SPRU FB0 TMS320x2833x,2823xSystemControlandInterr uptsReferenceGuidedescribesthevariousint erruptsandsystemcontrolfeaturesofthe2833 xdigitalsignalcontrollers(DSCs).

3 SPRUFZ5A August2008 TMS320x2833x,2823xAnalog-to-DigitalConve rter(ADC)ReferenceGuidedescribeshowtocon figureandusetheon-chipADCmodule, TMS320x2833x,2823xExternalInterface(XINT F)User'sGuidedescribestheXINTF,whichisan onmultiplexedasynchronousbus, TMS320x2833x,TMS320x2823xBootROMUser'sGu idedescribesthepurposeandfeaturesofthebo otloader(factory-programmedboot-loadings oftware) TMS320x2833x,2823xMultichannelBufferedSe rialPort(McBSP)User' TMS320x2833x,2823xDirectMemoryAccess(DMA ) TMS320x2833x,2823xEnhancedPulseWidthModu lator(ePWM)ModuleReferenceGuidedescribes themainareasoftheenhancedpulsewidthmodul atorthatincludedigitalmotorcontrol,switc hmodepowersupplycontrol,UPS(uninterrupti blepowersupplies), TMS320x2833x,2823xHigh-ResolutionPulseWi dthModulator(HRPWM)describestheoperation ofthehigh-resolutionextensiontothepulsew idthmodulator(HRPWM).SPRUFG4 TMS320x2833x,2823xEnhancedCapture(eCAP) TMS320x2833x,2823xEnhancedQuadratureEnco derPulse(eQEP)ReferenceGuidedescribesthe eQEPmodule,whichisusedforinterfacingwith alinearorrotaryincrementalencodertogetpo sition,direction, TMS320x2833x,2823xEnhancedControllerArea Network(eCAN) TMS320F2833x, 2823xSerialCommunicationInt erface(SCI)ReferenceGuidedescribestheSCI ,whichisatwo-wireasynchronousserialport, (NRZ) TMS320x2833x,2823xSerialPeripheralInterf ace(SPI)ReferenceGuidedescribestheSPI-ah igh-speedsynchronousserialinput/output(I /O)port-thatallowsaserialbitstreamofprog rammedlength(onetosixteenbits) TMS320x2833x,2823xInter-IntegratedCircui t(I2C)ReferenceGuidedescribesthefeatures andoperationoftheinter-integratedcircuit (I2C) SPRU513 TMS320C28xAssemblyLanguageToolsUser'sGui dedescribestheassemblylanguagetools(asse mblerandothertoolsusedtodevelopassemblyl anguagecode)

4 ,assemblerdirectives,macros,commonobject fileformat, TMS320C28xOptimizingCCompilerUser'sGuide describestheTMS320C28x C/C++ ++ TheTMS320C28xInstructionSetSimulatorTech nicalOverviewdescribesthesimulator,avail ablewithintheCodeComposerStudioforTMS320 C2000 IDE,thatsimulatestheinstructionsetoftheC 28x August2008 TMS320C28xDSP/BIOSA pplicationProgrammingInterface(API) , August2008 RevisedJuly2009 ReadThisFirst9 SubmitDocumentationFeedbackReadThisFirst 10 SPRUFZ5A August2008 RevisedJuly2009 SubmitDocumentationFeedbackChapter1 SPRUFZ5A August2008 RevisedJuly2009 OverviewTheserialcommunicationsinterface (SCI)isatwo wireasynchronousserialport, (NRZ) , , ,theSCIchecksreceiveddataforbreakdetecti on,parity,overrun, August2008 speedprescalerSystemcontrolblockPIEblock RXINTTXINTR egistersSCISCIAENCLKLSPCLKSCIRXDSCITXDGP IOMUXData : Twoexternalpins: SCITXD:SCItransmit-outputpin SCIRXD:SCIreceive-inputpinBothpinscanbeu sedasGPIO ifnotusedforSCI.

5 Baudrateprogrammableto64 Kdifferentrates Data-wordformat Onestartbit Data-wordlengthprogrammablefromonetoeigh tbits Optionaleven/odd/noparitybit Oneortwostopbits Fourerror-detectionflags:parity,overrun, framing,andbreakdetection Twowake-upmultiprocessormodes:idle-linea ndaddressbit Half-orfull-duplexoperation Double-bufferedreceiveandtransmitfunctio ns Transmitterandreceiveroperationscanbeacc omplishedthroughinterrupt-drivenorpolled algorithmswithstatusflags. Separateenablebitsfortransmitterandrecei verinterrupts(exceptBRKDT) NRZ(non-return-to-zero)format ,theregisterdataisinthelowerbyte(7 0),andtheupperbyte(15 8) August2008 RevisedJuly2009 SubmitDocumentationFeedbackTX FIFO _0 LSPCLKWUTF rame Format and ModeEven/OddEnableParitySCI RX Interrupt select INT TX Interrupt select logicTX INT ERR INT 0 SCIHBAUD. 15 8 Baud RateMSbyteRegisterSCILBAUD. 7 0 Transmitter DataBuffer RateLSbyteRegister RXSHFR egister FIFO _1 TX FIFO _158TX FIFO registersTX FIFO InterruptTX FIFO 0 Receive DataBuffer 0 RX FIFO_1RX FIFO _08RX FIFO InterruptLogicRXINTRX FIFO OERX 2To CPUTo baud detect.

6 Auto-baud-detecthardwarelogic 16- (SCI)ModuleBlockDiagramSPRUFZ5A August2008 (x16)DescriptionSCICCR0x0000-70501 SCI-ACommunicationsControlRegisterSCICTL 10x0000-70511 SCI-AControlRegister1 SCIHBAUD0x0000-70521 SCI-ABaudRegister,HighBitsSCILBAUD0x0000 -70531 SCI-ABaudRegister, (x16)Description(1)(2)SCICCR0x0000-77501 SCI-BCommunicationsControlRegisterSCICTL 10x0000-77511 SCI-BControlRegister1 SCIHBAUD0x0000-77521 SCI-BBaudRegister,HighBitsSCILBAUD0x0000 -77531 SCI-BBaudRegister,LowBitsSCICTL20x0000-7 7541 SCI-BControlRegister2 SCIRXST0x0000-77551 SCI-BReceiveStatusRegisterSCIRXEMU0x0000 -77561 SCI-BReceiveEmulationDataBufferRegisterS CIRXBUF0x0000-77571 SCI-BReceiveDataBufferRegisterSCITXBUF0x 0000-77591 SCI-BTransmitDataBufferRegisterSCIFFTX0x 0000-775A1 SCI-BFIFOT ransmitRegisterSCIFFRX0x0000-775B1 SCI-BFIFOR eceiveRegisterSCIFFCT0x0000-775C1 SCI-BFIFOC ontrolRegisterSCIPRI0x0000-775F1 SCI-BPriorityControlRegister(1) (2).

7 Atransmitter(TX)anditsmajorregisters(upp erhalfofFigure1-2) SCITXBUF (loadedbytheCPU)tobetransmitted TXSHF register ,onebitatatime Areceiver(RX)anditsmajorregisters(lowerh alfofFigure1-2) RXSHF register ,onebitatatime SCIRXBUF Aprogrammablebaudgenerator Data-memory-mappedcontrolandstatusregist ers14 OverviewSPRUFZ5A August2008 Stop4567 MSBS tartLSB23 Addr/dataParity4567 MSBStopIdle-line mode(Normal nonmultiprocessor Communications )Address-bit modeAddress ,theidle-linemultiprocessormode( )andtheaddress-bitmultiprocessormode( ). (UART) ( ) : Onestartbit Onetoeightdatabits Aneven/oddparitybitornoparitybit OneortwostopbitsSCIdata,bothreceiveandtr ansmit,isinNRZ(non-return-to-zero) ,showninFigure1-3,consistsof: Onestartbit Onetoeightdatabits Aneven/oddparitybit(optional) Oneortwostopbits Anextrabittodistinguishaddressesfromdata (address-bitmodeonly) ,oneortwostopbits, August2008 , (s) :0 Selectthecharacter(data)length(onetoeigh tbits).

8 , , , , (bit2ofSCICTL1) , ,itdoesnotsetRXRDY,RXINT,oranyoftherecei vererrorstatusbitsto1unlesstheaddressbyt eisdetectedandtheaddressbitinthereceived frameisa1(applicabletoaddress-bitmode).T heSCIdoesnotaltertheSLEEPbit; , : Theidle-linemode( ) Theaddress-bitmode( )addsanextrabit(thatis,anaddressbit) ,unliketheidlemode, ,atahightransmitspeed, (SCICCR,bit3).BothmodesusetheTXWAKE flagbit(SCICTL1,bit3),RXWAKE flagbit(SCIRXST,bit1),andtheSLEEP flagbit(SCICTL1,bit2) August2008 DataFirst frame within blockIs address; it follows idleperiod of 10 bits or moreFrame withinblockIdle periodless than 10bitsIdle period of 10 bitsor more Several blocks of framesData format(Pins SCIRXD, SCITXD)Data format expandedIdle periods of 10 bits or moreseparate the blocksStartStartStart One block of , ,theSCIportwakesupandrequestsaninterrupt (bitnumber1RX/BKINTENA-ofSCICTL2mustbeen abledtorequestaninterrupt).

9 Itreadsthefirstframeoftheblock, ,theCPUclearstheSLEEP bitandreadstherestoftheblock;ifnot, (ADDR/IDLEMODEbit=0), (bitspersecond).Theidle-linemultiprocess orcommunicationformatisshowninFigure1-4( ADDR/IDLEMODE bitisbit3ofSCICCR). (sentbyaremotetransmitter) , , August2008 (WUT)FlagTXWAKEWUTT ransmit buffer (SCITXBUF) :TheSCIportfirstsetstheTXWAKEbit(SCICTL1 ,bit3) ,theserialcommunicationslineisnotidleany longerthannecessary.(Adon tcarebytehastobewrittentoSCITXBUF aftersettingTXWAKE,andbeforesendingthead dress,soastotransmittheidletime.)Associa tedwiththeTXWAKE bitisthewake-uptemporary(WUT) , ,WUTisloadedfromTXWAKE, (contentnotimportant:adon tcare)totheSCITXBUF register(transmitdatabuffer)tosendablock -startsignal.(Thefirstdatawordwritteniss uppressedwhiletheblock-startsignalissent outandignoredafterthat.)WhentheTXSHF(tra nsmitshiftregister)isfreeagain,SCITXBUF contentsareshiftedtoTXSHF,theTXWAKE valueisshiftedtoWUT, ,thestart,data, t-caredatawordisshiftedtotheTXSHF register,theSCITXBUF(andTXWAKE ifnecessary) ,thereceiverneithersetsRXRDY northeerrorstatusbits, (ADDR/IDLEMODEbit=1), (seeFigure1-6).

10 ,whentheSCITXBUF registerandTXWAKE areloadedintotheTXSHF registerandWUTrespectively, , , ( August2008 RevisedJuly2009 SubmitDocumentationFeedbackMSBP arity01 AddrDataAddr Data format(Pins SCIRXD, SCITXD)Data format expandedFirst frame withinblock is address(Address bit is 1)1 Idle time is ofno significanceNext frame is addressfor next block(Address bit is 1)StartLSBStopAddress-bit mode frame exampleAddress bitFrame within block(Address bit is 0)1 StartStartStartOne blockIdle periods of no significanceBlocks of :Asageneralrule, (1foranaddressframe,0foradataframe) (oneway)ortwoline(twoway) ,theframeconsistsofastartbit,onetoeightd atabits,anoptionaleven/oddparitybit,ando neortwostopbits(showninFigure1-7). , , ,fifth,andsixthSCICLK periods,andbit-valuedeterminationisonama jority(twooutofthree) , August2008 RevisedJuly2009 Overview19 SubmitDocumentationFeedbackMajorityvoteS tart bitLSB of dataSC ICLK(internal)SCIRXD123456781234567818 SCICLK periods per data bit8 SCICLK periods per data : Address-bitwake-upmode(addressbitdoesnot appearinidle-linemode) (1)2)DataarrivesontheSCIRXDpin,startbitd etected.