TMS320x2833x, 2823x Inter-IntegratedCircuit (I2C) …

1 TMS320x2833x, 2823xInter-IntegratedCircui t (I2C) ModuleReferenceGuideLiteratureNumb er:SPRUG03 BAugust2008 RevisedJune20112 SPRUG03B August2008 RevisedJune2011 SubmitDocumentationFeedbackCopyright 2008 2011, (I2 CMDR).. (I2 CEMDR).. (I2 CIER).. (I2 CSTR).. (I2 CISRC).. (I2 CPSC).. (I2 CCLKLandI2 CCLKH).. (I2 CSAR).. (I2 COAR).. (I2 CCNT).. (I2 CDRR).. (I2 CDXR).. (I2 CFFTX).. (I2 CFFRX).. August2008 RevisedJune2011 TableofContentsSubmitDocumentationFeedba ckCopyright 2008 2011, (7-BitAddressingwith8-bitDataConfigurati onShown)..167I2 CModule7-BitAddressingFormat(FDF= 0,XA= 0 in I2 CMDR)..178I2 CModule10-BitAddressingFormat(FDF= 0,XA= 1 in I2 CMDR)..179I2 CModuleFreeDataFormat(FDF= 1 in I2 CMDR)..1710 RepeatedSTARTC ondition(inThisCase,7-BitAddressingForma t).. (I2 CMDR)..2315 PinDiagramShowingtheEffectsoftheDigitalL oopbackMode(DLB) (I2 CEMDR)..2617 BCMBit, (I2 CIER)..2819I2 CStatusRegister(I2 CSTR)..2920I2 CInterruptSourceRegister(I2 CISRC).

2 3221I2 CPrescalerRegister(I2 CPSC)..3222 TheRolesoftheClockDivide-DownValues(ICCL andICCH)..3323I2 CClockLow-TimeDividerRegister(I2 CCLKL)..3324I2 CClockHigh-TimeDividerRegister(I2 CCLKH)..3325I2 CSlaveAddressRegister(I2 CSAR)..3426I2 COwnAddressRegister(I2 COAR)..3427I2 CDataCountRegister(I2 CCNT)..3528I2 CDataReceiveRegister(I2 CDRR)..3529I2 CDataTransmitRegister(I2 CDXR)..3630I2 CTransmitFIFOR egister(I2 CFFTX)..3631I2 CReceiveFIFOR egister(I2 CFFRX)..374 ListofFiguresSPRUG03B August2008 RevisedJune2011 SubmitDocumentationFeedbackCopyright 2008 2011, (I2 CMDR) ,STT, (I2 CEMDR) (I2 CIER) (I2 CSTR) (I2 CISRC) (I2 CPSC) (I2 CCLKL) (I2 CCLKH) (I2 CSAR) (I2 COAR) (I2 CCNT) (I2 CDRR) (I2 CDXR) (I2 CFFTX) (I2 CFFRX) August2008 RevisedJune2011 ListofTablesSubmitDocumentationFeedbackC opyright 2008 2011,TexasInstrumentsIncorporated6 ListofTablesSPRUG03B August2008 RevisedJune2011 SubmitDocumentationFeedbackCopyright 2008 2011,TexasInstrumentsIncorporatedPreface SPRUG03B August2008 RevisedJune2011 ReadThisFirstAboutThisManualThismanualde scribesthefeaturesandoperationoftheinter -integratedcircuit (I2C) modulethatisavail ableontheTMS320x2833x,2823device.

3 TheI2 Cmoduleprovidesaninterfacebetweenoneofth ese28xdevicesanddevicescompliantwithPhil ipsSemiconductorsInter-ICbus(I2C-bus) thisreferenceguideis a Type0 ,28xxxDSPP eripheralReferenceGuide(SPRU566) fora listofalldeviceswithanI2 Cmoduleofthesametype,todeterminethediffe rencesbetweentypes,andfora listofdevice-specificdifferenceswithina ,thefollowingnumberis 40hexadecimal(decimal64):40h. Registersin thisdocumentareshownin figuresanddescribedin tables. Eachregisterfigureshowsa labeledwithitsbitname,itsbeginningandend ingbitnumbersabove, legendexplainsthenotationusedfortheprope rties. Reservedbitsin a registerfiguredesignatea bitthatis :Entertheliteraturenumberin SPRS439 TMS320F28335,TMS320F28334,TMS320F28332,T MS320F28235,TMS320F28234,TMS320F28232 DigitalSignalControllers(DSCs)DataManual containsthepinout,signaldescriptions,asw ellaselectricalandtimingspecificationsfo rtheF2833 TMS320F28335,TMS320F28334,TMS320F28332,T MS320F28235,TMS320F28234, 'sGuides SPRU430 TMS320C28xCPUandInstructionSetReferenceG uidedescribesthecentralprocessingunit(CP U)andtheassemblylanguageinstructionsofth eTMS320C28xfixed-pointdigitalsignalproce ssors(devices).

4 It SPRU566 TMS320x28xx,28xxxDSPP eripheralReferenceGuidedescribestheperip heralreferenceguidesofthe28xdigitalsigna lprocessors(DSPs).7 SPRUG03B August2008 RevisedJune2011 PrefaceSubmitDocumentationFeedbackCopyri ght 2008 2011, TMS320x2833x, 2823xSystemControlandInterr uptsReferenceGuidedescribesthevariousint erruptsandsystemcontrolfeaturesofthe2833 xand2823xdigitalsignalcontrollers(DSCs). SPRU812 TMS320x2833x, 2823xAnalog-to-DigitalConve rter(ADC)ReferenceGuidedescribeshowtocon figureandusetheon-chipADCmodule,whichis a TMS320x2833x, 2823xDSCE xternalInterface(XINTF)ReferenceGuidedes cribestheXINTF,whichis a nonmultiplexedasynchronousbus,asit is TMS320x2833x, 2823xBootROMR eferenceGuidedescribesthepurposeandfeatu resofthebootloader(factory-programmedboo t-loadingsoftware) alsodescribesothercontentsofthedeviceon- chipbootROMandidentifieswherealloftheinf ormationis TMS320x2833x, 2823xMultichannelBufferedSe rialPort(McBSP) deviceandotherdevicesin a TMS320x2833x, 2823xDirectMemoryAccess(DMA ) TMS320x2833x, 2823xEnhancedPulseWidthModu lator(ePWM)ModuleReferenceGuidedescribes themainareasoftheenhancedpulsewidthmodul atorthatincludedigitalmotorcontrol,switc hmodepowersupplycontrol,UPS(uninterrupti blepowersupplies), TMS320x2833x, 2823xHigh-ResolutionPulseWi dthModulator(HRPWM)

5 ReferenceGuidedescribestheoperationofthe high-resolutionextensiontothepulsewidthm odulator(HRPWM).SPRUFG4 TMS320x2833x, 2823xEnhancedCapture(eCAP) TMS320x2833x, 2823xEnhancedQuadratureEnco derPulse(eQEP)ModuleReferenceGuidedescri bestheeQEPmodule,whichis usedforinterfacingwitha linearorrotaryincrementalencodertogetpos ition,direction,andspeedinformationfroma TMS320x2833x, 2823xEnhancedControllerArea Network(eCAN) TMS320x2833x, 2823xSerialCommunicationsIn terface(SCI)ReferenceGuidedescribestheSC I,whichis a two-wireasynchronousserialport,commonlyk nownasa (NRZ) TMS320x2833x, 2823xDSCS erialPeripheralInterface(SPI)ReferenceGu idedescribestheSPI- a high-speedsynchronousserialinput/output( I/O)port- thatallowsa serialbitstreamofprogrammedlength(onetos ixteenbits) TMS320x2833x, 2823xInter-IntegratedCircui t (I2C) ModuleReferenceGuidedescribesthefe aturesandoperationoftheinter-integratedc ircuit(I2C) SPRU513 'sGuidedescribestheassemblylanguagetools (assemblerandothertoolsusedtodevelopasse mblylanguagecode)

6 ,assemblerdirectives,macros,commonobject fileformat, August2008 RevisedJune2011 SubmitDocumentationFeedbackCopyright 2008 2011, TMS320C28xOptimizingC/C++ 'sGuidedescribestheTMS320C28x C/C++ ++ TMS320C28xInstructionSetSimulatorTechnic alOverviewdescribesthesimulator,availabl ewithintheCodeComposerStudioforTMS320C20 00 IDE,thatsimulatestheinstructionsetoftheC 28x TMS320C28 (API) , August2008 RevisedJune2011 ReadThisFirstSubmitDocumentationFeedback Copyright 2008 2011,TexasInstrumentsIncorporated10 ReadThisFirstSPRUG03B August2008 RevisedJune2011 SubmitDocumentationFeedbackCopyright 2008 2011,TexasInstrumentsIncorporated28xI2CI 2 CEPROMI2CI2C28xVDDP ullupresistorsSerial data (SDA)Serial clock (SCL)controllerReferenceGuideSPRUG03B August2008 RevisedJune2011 TMS320x280xInter-IntegratedCircuitModule Thisguidedescribesthefeaturesandoperatio noftheinter-integratedcircuit (I2C) module thatis availableontheTMS320x280xdigitalsignalpr ocessor(device).

7 TheI2 Cmoduleprovidesaninterfacebetweenoneofth esedevicesanddevicescompliantwithPhilips SemiconductorsInter-ICbus(I2C-bus) to8- :A unitofdatatransmittedorreceivedbytheI2 Cmodulecanhavefewerthan8 bits;however,forconvenience,a unitofdatais calleda databytethroughoutthisdocument.(Thenumbe rofbitsin a databyteis selectableviatheBCbitsofthemoderegister, I2 CMDR.)Thisreferenceguideis showsanexampleofmultipleI2 Cmodulesconnectedfora August2008 RevisedJune2011 TMS320x280xInter-IntegratedCircuitModule SubmitDocumentationFeedbackCopyright 2008 2011, : CompliancewiththePhilipsSemiconductorsI2 C-busspecification( ): Supportfor8-bitformattransfers 7-bitand10-bitaddressingmodes Generalcall START bytemode Supportformultiplemaster-transmittersand slave-receivers Supportformultipleslave-transmittersandm aster-receivers Combinedmastertransmit/receiveandreceive /transmitmode Datatransferrateoffrom10kbpsupto400kbps( PhilipsFast-moderate) One16-bytereceiveFIFO andone16-bytetransmitFIFO resultofoneofthefollowingconditions:tran smit-dataready,receive-dataready,registe r-accessready,no-acknowledgmentreceived, arbitrationlost,stopconditiondetected,ad dressedasslave.

8 AnadditionalinterruptthatcanbeusedbytheC PUwhenin FIFO mode Moduleenable/disablecapability : High-speedmode(Hs-mode) recognizedbya transmitterora receiver, masterdeviceis thedevicethatinitiatesa ,anydeviceaddressedbythismasteris considereda ,in ,theI2 Cmodulehasa serialdatapin(SDA)anda serialclockpin(SCL),asshownin Figure2. positivesupplyvoltageusinga free, : StandardMode:Sendexactlyn datavalues,wheren is a valueyouprogramin forregisterinformation. RepeatMode:Keepsendingdatavaluesuntilyou usesoftwaretoinitiatea STOP conditionora : A serialinterface:onedatapin(SDA)andoneclo ckpin(SCL) DataregistersandFIFO stotemporarilyholdreceivedataandtransmit datatravelingbetweentheSDApinandtheCPU Controlandstatusregisters A peripheralbusinterfacetoenabletheCPUtoac cesstheI2 CmoduleregistersandFIFOs. A clocksynchronizertosynchronizetheI2 Cinputclock(fromthedeviceclockgenerator) andtheclockontheSCLpin,andtosynchronized atatransferswithmastersofdifferentclocks peeds12 TMS320x280xInter-IntegratedCircuitModule SPRUG03B August2008 RevisedJune2011 SubmitDocumentationFeedbackCopyright 2008 2011,TexasInstrumentsIncorporatedI2 CXSRI2 CDXRI2 CRSRI2 CDRRC locksynchronizerPrescalerNoise filtersArbitratorI2C INTP eripheral busInterrupt toCPU/PIESDASCLC ontrol/statusregistersCPUI2C moduleTX FIFORX FIFOFIFO Interruptto A prescalertodividedowntheinputclockthatis driventotheI2 Cmodule A noisefilteroneachofthetwopins,SDAandSCL Anarbitratortohandlearbitrationbetweenth eI2 Cmodule(whenit is a master)

9 Andanothermaster Interruptgenerationlogic,sothataninterru ptcanbesenttotheCPU FIFO interruptgenerationlogic,sothatFIFO accesscanbesynchronizedtodatareceptionan ddatatransmissionin theI2 CmoduleFigure2 showsthefourregistersusedfortransmission andreceptionin transmitter,datawrittentoI2 CDXRis copiedtoI2 CXSR andshiftedoutontheSDApinonebita configuredasa receiver,receiveddatais Figure3, thedeviceclockgeneratorreceivesa signalfromanexternalclocksourceandproduc esanI2 Cinputclockwitha equivalenttotheCPUclockandis August2008 RevisedJune2011 TMS320x280xInter-IntegratedCircuitModule SubmitDocumentationFeedbackCopyright 2008 2011,TexasInstrumentsIncorporated28x devicedividerPLLCRICCHIPSCI C input clock(SYSCLKOUT)2 Device input clockModule clockfor I2C module operationMaster clockon SCL pinI2C moduleICCL,To I2C-bus module clock frequency+I2C input clock frequency(IPSC)1) programmableprescalerin ,initializetheIPSC fieldoftheprescalerregister, :NOTE:TomeetalloftheI2 Cprotocoltimingspecifications,themodulec lockmustbeconfiguredbetween7 - in theresetstate(IRS= 0 in I2 CMDR).

10 Theprescaledfrequencytakeseffectonlywhen IRSis configuredtobea Figure3, a secondclockdividerin is varietyofdifferenttechnologydevicesthatc anbeconnectedtotheI2C-bus,thelevelsoflog ic0 (low)andlogic1(high)arenotfixedanddepend ontheassociatedlevelofVDD. Fordetails, (seeFigure4). Thehighorlowstateofthedataline,SDA,shoul dchangeonlywhentheclocksignalonSCLis August2008 RevisedJune2011 SubmitDocumentationFeedbackCopyright 2008 2011,TexasInstrumentsIncorporatedData linestable dataChange of masterandasa theI2 Cmoduleis a master,it beginsasa ,theI2 Cmodulemustremaina slave, theI2 Cmoduleis a slave,it beginsasa slave-receiverandtypicallysendsacknowled gmentwhenitrecognizesitsslaveaddressfrom a themasterwillbesendingdatatotheI2 Cmodule,themodulemustremaina themasterhasrequesteddatafromtheI2 Cmodule, a slaveandreceivesdatafroma ,serialdatabitsreceivedonSDAareshiftedin slave,theI2 Cmoduledoesnotgeneratetheclocksignal,but it canholdSCLlowwhiletheinterventionofthede viceisrequired(RSFULL= 1 in I2 CSTR)aftera a slaveandtransmitsdatatoa.