TPS3808 Low-Quiescent-Current, Programmable-Delay ...

1 TPS3808 Low-Quiescent-Current, Programmable-Delay Supervisory Circuit1 Features Power-On Reset Generator with Adjustable DelayTime: ms to 10 s Very Low Quiescent Current: A Typical High Threshold Accuracy: Typ Fixed Threshold Voltages for Standard VoltageRails from V to 5 V and Adjustable VoltageDown to V Are Available Manual Reset ( MR) Input Open-Drain RESET Output Temperature Range: 40 C to 125 C Small SOT-23 and 2-mm 2-mm WSONP ackages2 Applications DSP or Microcontroller Applications Notebook and Desktop Computers PDAs and Hand-Held Products Portable and Battery-Powered Products FPGA and ASIC Applications3 DescriptionThe TPS3808 family of microprocessor supervisorycircuits monitors system voltages from V to 5 V,asserting an open-drain RESET signal when theSENSE voltage drops below a preset threshold orwhen the manual reset ( MR) pin drops to a logic RESET output remains low for the user-adjustable delay time after the SENSE voltage andmanual reset ( MR) return above the TPS3808 device uses a precision reference toachieve threshold accuracy for VIT V.

2 Thereset delay time can be set to 20 ms by disconnectingthe CT pin, 300 ms by connecting the CT pin to VDDusing a resistor, or can be user-adjusted ms and 10 s by connecting the CT pin to anexternal capacitor. The TPS3808 device has a verylow typical quiescent current of A, so it is well-suited to battery-powered applications. It is availablein the SOT-23 and 2-mm 2-mm WSON packages,and is fully specified over a temperature range of 40 C to 125 C (TJ).Device InformationPART NUMBERPACKAGE (1)BODY SIZE (NOM) TPS3808 SOT-23 (6) mm x mmWSON (6) mm x mm(1) For all available packages, see the orderable addendum atthe end of the data VTPS3808G12 TPS3808G33 DSPSENSEVDDVDDSENSEVI/OVCOREGPIOGNDGNDGN DRESETMRCTCTRESETT ypical (V)DDI ( A)DDm-40 C 25 C85 C125 C Supply Current vs Supply MAY 2004 REVISED SEPTEMBER 2020 Copyright 2020 Texas Instruments IncorporatedSubmit Document Feedback1 Product Folder Links: TPS3808 TPS3808 SBVS050L MAY 2004 REVISED SEPTEMBER 2020An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers.

3 PRODUCTION of Contents1 Revision Device Voltage Pin Configuration and Absolute Maximum ESD Recommended Operating Thermal Electrical Switching Typical Detailed Functional Block Feature Device Functional Application and Application Typical Power Supply Layout Layout Device and Documentation Device Documentation Support Electrostatic Discharge Mechanical, Packaging, and Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current from Revision K (October 2015) to Revision L (September 2020)Page Updated the numbering format for tables, figures and cross-references throughout the from Revision J (August 2008) to Revision K (October 2015)Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application andImplementation section, Power Supply Recommendations section, Layout section, Device andDocumentation Support section, and Mechanical, Packaging, and Orderable Information section.

4 MovedSwitching Characteristics table, timing diagram, and related truth Changed Figure 9-1; removed capacitor shown on CT ..14 TPS3808 SBVS050L MAY 2004 REVISED SEPTEMBER Document FeedbackCopyright 2020 Texas Instruments IncorporatedProduct Folder Links: TPS38085 Device Voltage ThresholdsThe following table shows the nominal rail to be monitored and the corresponding threshold voltage of NUMBERNOMINAL SUPPLY VOLTAGE(1)THRESHOLD VOLTAGE (VIT) VTPS3808G303 VTPS3808G505 V(1) Custom threshold voltages from V to V, V to 5 V are available through the use offactory EEPROM programming. Minimum order quantities apply. Contact the factory for details MAY 2004 REVISED SEPTEMBER 2020 Copyright 2020 Texas Instruments IncorporatedSubmit Document Feedback3 Product Folder Links: TPS38086 Pin Configuration and Functions123654 RESETGNDMRCTSENSEVDDF igure 6-1. DBV Package 6-Pin SOT-23 Top View654123 RESETGNDMRCTSENSEVDDTHERMALPADF igure 6-2.

5 DRV Package 6-Pin ( mm ) WSON With Thermal Pad Top ViewTable 6-1. Pin FunctionsPINI/ODESCRIPTIONNAMESOT-23 WSONCT43 IReset period programming pin. Connecting this pin to VDD through a 40-k to 200-k resistor or leaving it open results in fixed delay times (see Section ). Connecting thispin to a ground referenced capacitor 100 pF gives a user-programmable delay Section for more GroundMR34 IDriving the manual reset pin ( MR) low asserts RESET. MR is internally tied to VDD by a 90-k pull-up is an open-drain output that is driven to a low-impedance state when RESET isasserted (either the SENSE input is lower than the threshold voltage (VIT) or the MR pin isset to a logic low). RESET remains low (asserted) for the reset period after both SENSE isabove VIT and MR is set to a logic high. A pull-up resistor from 10 k to 1 M should beused on this pin, and allows the reset pin to attain voltages higher than pin is connected to the voltage to be monitored.

6 If the voltage at this terminal dropsbelow the threshold voltage VIT, then RESET is voltage. It is good analog design practice to place a F ceramic capacitorclose to this Pad Thermal Pad. Connect to ground plane to enhance thermal performance of MAY 2004 REVISED SEPTEMBER Document FeedbackCopyright 2020 Texas Instruments IncorporatedProduct Folder Links: TPS38087 Absolute Maximum Ratingsover operating junction temperature range (unless otherwise noted) (1)MINMAXUNITV oltageVDD + , VMR, VSENSE pin 55mATemperatureOperating junction, TJ (2) 40150 CStorage, Tstg 65150 C(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated underRecommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect devicereliability.

7 (2) As a result of the low dissipated power in this device, it is assumed that TJ = ESD RatingsVALUEUNITV(ESD)Electrostatic dischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001,all pins(1) 2000 VCharged device model (CDM), per JEDEC specificationJESD22-C101, all pins(2) 500(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted)MINNOMMAXUNITVDDI nput supply pin (Ct)CT pin voltageVDDVV MRMR pin RESETRESET pin RESETRESET pin Thermal InformationTHERMAL METRIC(1) TPS3808 UNITDBV (SOT-23)DRV (WSON)6 PINS6 PINSR JAJunction-to-ambient thermal C/WR JC(top)Junction-to-case (top) thermal C/WR JBJunction-to-board thermal C/W JTJunction-to-top characterization C/W JBJunction-to-board characterization C/WR JC(bot)Junction-to-case (bottom) thermal C/W(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport, MAY 2004 REVISED SEPTEMBER 2020 Copyright 2020 Texas Instruments IncorporatedSubmit Document Feedback5 Product Folder Links.

8 Electrical V VDD V, RLRESET = 100 k , CLRESET = 50 pF, over operating temperature range (TJ = 40 C to125 C), unless otherwise noted. Typical values are at TJ = 25 C(1).PARAMETERTEST CONDITIONSMINTYPMAXUNITVDDI nput supply range 40 C < TJ < 125 C < TJ < 85 current (current into VDD pin)VDD = V, RESET not assertedMR, RESET, CT AVDD = V, RESET not assertedMR, RESET, CT output V VDD < V, IOL = V VDD V, IOL = 1 reset voltage(2)VOL (max) = V, I RESET = 15 inputthreshold accuracyTPS3808G01 2% 1%2%VIT V V < VIT V 2% 1%2%VIT V 40 C < TJ < 85 C V < VIT V 40 C < TJ < 85 C on VIT versions1% MRMR Internal pullup resistance7090k ISENSEI nput current atSENSE pinTPS3808G01 VSENSE = VIT 2525nAFixed versionsVSENSE = AIOHRESET leakage currentV RESET = V, RESET not asserted300nACINI nput capacitance, anypinCT pinVIN = 0 V to VDD5pFOther pinsVIN = 0 V to V5 VILMR logic low VDDVVIHMR logic high VDDVDD(1) The lowest supply voltage (VDD) at which RESET becomes active.

9 Trise(VDD) 15 s/V.(2) RLRESET and CLRESET are the resistor and capacitor connected to the RESET MAY 2004 REVISED SEPTEMBER Document FeedbackCopyright 2020 Texas Instruments IncorporatedProduct Folder Links: Switching V VDD V, RLRESET = 100 k , CLRESET = 50 pF, over operating temperature range (TJ = 40 C to125 C), unless otherwise noted. Typical values are at TJ = 25 C.(1)PARAMETERTEST CONDITIONSMINTYPMAXUNITtwInput pulse width toRESETSENSEVIH = VIT, VIL = VIT20 sMRVIH = VDD, VIL = delay timeCT = OpenSee Figure 7-1122028msCT = VDD180300420CT = 100 = 180 delayMR to RESETVIH = VDD, VIL = VDD150nsHigh-to-low level RESET delaySENSE to RESETVIH = VIT, VIL = VIT20 s(1) RLRESET and CLRESET are the resistor and capacitor connected to the RESET + Reset Delay= Undefined StateFigure 7-1. TPS3808 Timing Diagram Showing MR and SENSE Reset MAY 2004 REVISED SEPTEMBER 2020 Copyright 2020 Texas Instruments IncorporatedSubmit Document Feedback7 Product Folder Links: Typical CharacteristicsAt TJ = 25 C, VDD = V, RLRESET = 100 k , and CLRESET = 50 pF, unless otherwise 40 C+25 C+85 C+125 CIDD( A)mVDD(V)Figure 7-2.

10 Supply Current vs Supply (mF)101 40 C, +25 C, +125 CRESETT imeout (sec)Figure 7-3. RESET Time-Out Period vs CT10864201030507090110130 Temperature ( C) 50 30 10 10 8 6 4 2 Normalized RESETT imeout Period (%)Figure 7-4. Normalized RESET Time-Out Period vsTemperature (CT = Open, CT = VDD, CT = Any)1001010510152030354525 Overdrive (%VIT)5040 Transient Durationbelow VIT(ms)RESET OCCURSABOVE THE CURVEF igure 7-5. Maximum Transient Duration at Sensevs Sense Threshold Overdrive ( C) 50 30 10 VIT(%)Figure 7-6. Normalized Sense Threshold Voltage(VIT) vs Level RESET Voltage (V)VDD= VRESET Current (mA)Figure 7-7. Low-Level RESET Voltage vs RESETC urrentTPS3808 SBVS050L MAY 2004 REVISED SEPTEMBER Document FeedbackCopyright 2020 Texas Instruments IncorporatedProduct Folder Links: TPS38080 Level RESET Voltage (V)RESET Current (mA)VDD= VVDD= VFigure 7-8. Low-Level RESET Voltage vs RESET MAY 2004 REVISED SEPTEMBER 2020 Copyright 2020 Texas Instruments IncorporatedSubmit Document Feedback9 Product Folder Links: TPS38088 Detailed OverviewThe TPS3808 microprocessor supervisory product family is designed to assert a RESET signal when either theSENSE pin voltage drops below VIT or the manual reset ( MR) is driven low.