UCC2891-94 - TI.com

1 SLUS542F OCTOBER 2003 REVISED JULY 2009 Output JitterDSoft Stop Shutdown of MAIN and AUXDI deal for Active Clamp/Reset Forward,Flyback ConvertersDProvides Complementary Auxiliary Driverwith Programmable Deadtime (Turn-OnDelay) between AUX and MAIN SwitchesDPeak Current-Mode Control withCycle-by-Cycle Current LimitingD110-V Input Startup Regulator on UCC2891/3 DTrueDrivet 2-A Sink, 2-A Source OutputsDAccurate Line UV and Line OV ThresholdDProgrammable Slope Synchronizable OscillatorDPrecise Programmable Maximum Duty CycleDProgrammable Soft Start APPLICATIONSD150-W to 700-W SMPSDHigh-Efficiency, Low EMI/RFI Off-Line orDC/DC ConvertersDServer, 48-V Telecom, DatacomDHigh Power Adapter, LCD-TV and PDP-TVDESCRIPTIONThe UCC2891/2/3/4 family of PWM controllers isdesigned to simplify implementation of the variousactive clamp/reset switching power UCC289x is a peak current-mode, fixed-frequency, high-performance pulse width includes the logic and the drive capability for theauxiliary switch with a simple method ofprogramming the critical delays for proper activeclamp UCC2891/3 includes a 110-V start-upregulator for initial start-up and to providekeep-alive power during features include an internalprogrammable slope compensation circuit,precise DMAX limit, and a single resistorprogrammable synchronizable oscillator.

2 Anaccurate line monitoring function also programsthe converter s ON and OFF transitions withregard to the bulk input voltage. Along with theUCC2897, this UCC289x family allows the powersupply designer to eliminate many of the externalcomponents, reducing the size and complexity ofthe UVOUTAUXPGND4 VREF11 VINUCC28916 GND7CS8 RSLOPE14 VDDSS/SD10FB9 SECONDARYSIDE E/AQ1Q2 LOADSRDRIVEBIASWINDING+VIND3Q3D4Q4 LoCoD2D1 RDELRONROFFRSLOPERFCFCVREFCBIASCSSCAUXCC LAMPCBULKROUTRCSDAUX ! " #$ % ! " &$'( # ! ) !%* )$#!" # ! "&%# # ! " &% !+% !% " %, " "! $ % !""! ) ) - !.* )$#! & #%"" / ) %" ! %#%"" (. #($)%!%"! / (( & %!% "*Copyright 2003 2009, Texas Instruments IncorporatedPlease be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SLUS542F OCTOBER 2003 REVISED JULY devices have limited built-in ESD protection.

3 The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1)UNITLine input voltage, VIN120 VSupply voltage, VDD(IDD < 10 mA) inputsFB, CS, SYNC, LINEOV, LINEUV to (VREF + )not to exceed 6 VOutput source current (peak), IO_SOURCEOUT, sink current (peak), IO_SINKOUT, AUX junction temperature range, TJ 55 to 150 CStorage temperature, Tstg 65 to 150 CESD ratingHuman body model, (HBM)2000 VESD ratingChange device model (CDM)500 VLead temperature, Tsol, 1,6 mm (1/16 inch) from case for 10 seconds300 C(1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions isnot implied.

4 Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect toGND. Currents are positive into and negative out of, the specified OPERATING CONDITIONSMINNOMMAXUNITLine input voltage, VIN18110 VSupply voltage, bypass capacitance1 FTiming resistance, RON = ROFF (for 250-kHzoperation)75k Operating junction temperature, TJ 40105 CReference bypass capacitance, FORDERING INFORMATIONPART NUMBERSTAAPPLICATIONAUXOUTPUTPOLARITYCST HRESHOLD(INCLUDESSLOPE COM-PENSATION)110-V START-UPCIRCUITSOIC 16(D)TSSOP 16(PW)DC VYe sUCC2891 DUCC2891PW 40 C to 125 CDC-DC/Sec. VNoUCC2892 DUCC2892PW 40 C to 125 CDC VYe sUCC2893 DUCC2893 PWOff VNoUCC2894 DUCC2894PW The D and PW packages are available taped and reeled. Add R suffix to device type ( UCC2891DR) to order quantities of 2,500devices per reel (for the D package) and 2,000 devices per reel (for the PW package). Bulk quantities are 40 units per tube (for the Dpackage) and 90 units per tube (for the PW package).

5 SLUS542F OCTOBER 2003 REVISED JULY RESISTANCE INFORMATIONPACKAGETHERMAL RESISTANCEUNITSSOIC 16 (D) to C/WSOIC 16 (D) ja (0 LFM) to C/WTSSOP 16 (PW) to C/WTSSOP 16 (PW) ja (0 LFM) to C/WPIN ASSIGNMENTSRTDELRTONRTOFFVREFSYNCGNDCSRS LOPELINEOVLINEUVVDDOUTAUXPGNDSS/SDFB1234 5678161514131211109 UCC2892 AND UCC2894D AND PW PACKAGE(TOP VIEW)RTDELRTONRTOFFVREFSYNCGNDCSRSLOPEVI NLINEUVVDDOUTAUXPGNDSS/SDFB1234 5678161514131211109 UCC2891 AND UCC2893D and PW PACKAGEs(TOP VIEW)ELECTRICAL CHARACTERISTICS VDD = 12 V(1), 1- F capacitor from VDD to GND, F capacitor from VREF to GND, RON = ROFF = 75 k , RDEL = 10 k ,RSLOPE = 50 k , 40 C TA = TJ 125 C (unless otherwise noted)PARAMETERTEST CONDITIONSMINTYPMAXUNITOVERALLISTARTUPS tart-up currentVDD < VUVLO300500 AIDDO perating supply current(1)(2)VFB = 0 V, VCS = 0 V,Outputs not switching23mAHIGH-VOLTAGE BIAS SECTION (UCC2891, UCC2893)IDD STVDD startup currentCurrent available from VDD during Start-up, VIN = 36 V, TA = 40 C to 85 C (3)411mAIVINJFET leakage currentVIN = 120 V; VDD = 14 V75 AUNDERVOLTAGE LOCKOUTS tart threshold voltage(1) operating voltage after MONITORVLINEUVLine UV and Line OV voltage UV and Line OV hysteresis ASOFT-STARTISSC harge currentRTON = 75 k currentRTON = 75 k AVSS/SDDischarge/shutdown threshold (1)Set VDD above the start threshold before setting at 12 V.

6 (2)Does not include current of the external oscillator network.(3)The power supply starts with IDD ST load on VDD, part will start up with no load up to 125 C. For more detailed information, see pin descriptionsfor VIN and VDD.(4)ISSC and ISS/SD are directly proportional to IRON. See equation 7. SLUS542F OCTOBER 2003 REVISED JULY CHARACTERISTICS VDD = 12 V(1), 1- F capacitor from VDD to GND, F capacitor from VREF to GND, RON = ROFF = 75 k , RDEL = 10 k ,RSLOPE = 50 k , 40 C TA = TJ 125 C (unless otherwise noted)PARAMETERTEST CONDITIONSMINTYPMAXUNITV oltage ReferenceVREFR eference voltageTJ = 25 voltage0 A < IREF < 5 mA, over circuit currentREF = 0 V, TJ = 25 C 20 11 8mAINTERNAL SLOPE COMPENSATIONmSlope(3)FB = High-10%RCSRSLOPE+10%OSCILLATORfOSCO scillator frequencyTJ = 25 C237250263kHzTotal variation 40 C < TJ 125 C; V < V225270kHzTotal variation 40 C < TJ 125 C; V < V225270kHzVP_POscillator amplitude (peak-to-peak)2 VSYNCHRONIZATIONVSYNCHSYNC theshold delay50nsPWMM aximum duty cycle66%70%74%Minimum duty cycle0%PWM offsetCS = 0 SENSEVLVLC urrent sense level shift (max)Maximum voltage error (clamped) sense sense (1)Set VDD above the start threshold before setting at 12 V.

7 (2)Does not include current of the external oscillator network. SLUS542F OCTOBER 2003 REVISED JULY CHARACTERISTICS VDD = 12 V(1), 1- F capacitor from VDD to GND, F capacitor from VREF to GND, RON = ROFF = 75 k , RDEL = 10 k ,RSLOPE = 50 k , 40 C TA = TJ 125 C (unless otherwise noted)PARAMETERTEST CONDITIONSMINTYPMAXUNITOUTPUT (OUT AND AUX)tRRise timeCLOAD = 2 nF1928tFFall timeCLOAD = 2 nF1423nstDEL1 Delay time (AUX to OUT)CLOAD = 2 nF, RDEL = 10 k 110nstDEL2 Delay time (OUT to AUX)CLOAD = 2 nF, RDEL = 10 k 115 IOUT(src)Output source current 2 AIOUT(sink)Output sink current2 AVOUT(low)Low-level output voltageIOUT = 150 (high)High-level output voltageIOUT = 150 (N channel)(P channel)50%50%50%50%50%50%Figure 1. Output Timing Diagram SLUS542F OCTOBER 2003 REVISED JULY BLOCK DIAGRAM123416151413 VIN (UCC2891/3)LINEOV (UCC2892/4)LINEUVVDDOUTRDELRTONRTOFFVREF 5678 SYNCGNDCSRSLOPE1211109 AUXPGNDSS/SDFBIRDELSYNCCLOCKREFGENVDD5 * ISLOPEVREFISLOPECT++3 * RSQQRPWMOFFTURN ONDELAYTURN ONDELAYIRDELVREFVREF2 * R++PWM VOUT1 * IRDELVREF+UCC2892/4 UCC2891 * IRDELVREF+ V+VDD13 V/ 8 VOUTVDDVDD93/94N +92/9491/9391/92P OFFUV OFF1 DMAXTYP: VREF = V75k1/2 x VREF1/2 x VREF1/2 x VREFIRTONIRDELISS = x IRTON SLUS542F OCTOBER 2003 REVISED JULY FUNCTIONSTERMINALNAMEUCC2891 UCC2893 UCC2892 UCC2894I/ODESCRIPTIONAUX1212 OThis output drives the auxiliary clamp MOSFET which is turned on when the main PWMswitching device is turned off.

8 The AUX pin can directly drive the auxiliary switch with 2-Asource turn-on current and 2-A sink turn-off pin is used to sense the peak current utilized for current mode control and for currentlimiting functions. The peak signal which can be applied to this pin before pulse-by-pulsecurrent limiting activates is approximately V for the UCC2891 and UCC2893 and Vfor the UCC2892 and pin is used to bring the error signal from an external optocoupler or error amplifier intothe PWM control circuitry. Often, there is a resistor tied from FB to VREF, and an optocoup-ler is used to pull the control pin closer to GND to reduce the pulse width of the OUT outputdriving the main power switch of the This pin serves as the fundamental analog ground for the PWM control circuitry. This pinshould be connected to PGND directly at the 16 IFor the UCC2892/4, provides the LINE overvoltage pin provides a means to accurately enable/disable the power converter stage by moni-toring the bulk input voltage or another parameter.

9 When the circuit initially starts (or restartsfrom a disabled condition), a rising input on LINEUV enables the outputs when the thresholdof V is crossed. After the circuit is enabled, then a falling LINEUV signal disables theoutputs when the same threshold is reached. The hysteresis between the two levels is pro-grammed using an internal current output pin drives the main PWM switching element MOSFET in an active clamp control-ler. It can directly drive an N-channel device with 2-A source turn-on current and 2-A sinkturn-off current. A 10 k resistor is recommended to connect this pin to The PGND should serve as the current return for the high-current output drivers OUT andAUX. Ideally, the current path from the outputs to the switching devices, and back would beas short as possible, and enclose a minimal loop resistor connected from this pin to GND programs an internal current source that sets theslope compensation ramp for the current mode control resistor from this pin to GND programs the turn-on delay of the two gate drive outputs toaccommodate the resonant transitions of the active clamp power resistor connected from this pin to GND programs an internal current source that dis-charges the internal timing resistor connected from this pin to GND programs an internal current source that chargesthe internal timing capacitor from SS/SD to ground is charged by an internal current source of IRTON to pro-gram the soft-start interval for the controller.

10 During a fault condition this capacitor is dis-charged by a current source equal to SYNC pin serves as a unidirectional synchronization input for the internal oscillator. Thesynchronization function is implemented such that the user programmable maximum dutycycle (set by RTON and RTOFF) remains accurate during synchronized is the power supply for the device. There should be a 1- F capacitor directly from VDDto PGND. The capacitor value should be minimum 10 times greater than that on and GND should be connected externally and directly from PGND to IFor the UCC2891 and UCC2893, this pin is connected to the input power rail directly. Insidethe device, a high-voltage start-up device is utilized to provide the start-up current for thecontroller until a bootstrap type bias rail becomes is the 5-V reference voltage that can be utilized for an external load of up to 5 this reference provides the supply rail for internal logic, it should be bypassed toAGND as close as possible to the device.