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UCx84x Current-Mode PWM Controllers - Texas Instruments

UCx84x Current-Mode PWM Controllers1 Features Optimized for off-line and DC-to-DC converters Low start-up current (< 1 mA) Automatic feedforward compensation Pulse-by-pulse current limiting Enhanced load-response characteristics Undervoltage lockout with hysteresis Double-pulse suppression High-current totem-pole output Internally trimmed bandgap reference Up to 500-kHz operation Error amplifier with low output resistance2 Applications Switching regulators of any polarity Transformer-coupled DC-DC converters3 DescriptionThe UCx84x series of control integrated circuits provide the features that are necessary to implement off-line or DC-to-DC fixed-frequency

do not have this pin, the gate driver is biased from the VCC pin. VC must have a bypass capacitor at least 10 times greater than the gate capacitance of the main switching FET used in the design. VCC 7 12 18 I Analog controller bias input that provides power to the device. Total VCC current is the sum of the quiescent VCC current and the

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Transcription of UCx84x Current-Mode PWM Controllers - Texas Instruments

1 UCx84x Current-Mode PWM Controllers1 Features Optimized for off-line and DC-to-DC converters Low start-up current (< 1 mA) Automatic feedforward compensation Pulse-by-pulse current limiting Enhanced load-response characteristics Undervoltage lockout with hysteresis Double-pulse suppression High-current totem-pole output Internally trimmed bandgap reference Up to 500-kHz operation Error amplifier with low output resistance2 Applications Switching regulators of any polarity Transformer-coupled DC-DC converters3 DescriptionThe UCx84x series of control integrated circuits provide the features that are necessary to implement off-line or DC-to-DC fixed-frequency

2 Current-Mode control schemes, with a minimum number of external components. The internally implemented circuits include an undervoltage lockout (UVLO), featuring a start-up current of less than 1 mA, and a precision reference trimmed for accuracy at the error amplifier input. Other internal circuits include logic to ensure latched operation, a pulse-width modulation (PWM) comparator that also provides current-limit control, and a totem-pole output stage that is designed to source or sink high-peak current. The output stage, suitable for driving N-channel MOSFETs, is low when it is in the off UCx84x family offers a variety of package options, temperature range options, choice of maximum duty cycle, and choice of turnon and turnoff thresholds and hysteresis ranges.

3 Devices with higher turnon or turnoff hysteresis are ideal choices for off-line power supplies, while the devices with a narrower hysteresis range are suited for DC-DC applications. The UC184x devices are specified for operation from 55 C to 125 C, the UC284x series is specified for operation from 40 C to 85 C, and the UC384x series is specified for operation from 0 C to 70 Information(1) PART NUMBERPACKAGE (PIN)BODY SIZE (NOM)UC184xCDIP (8) mm mmLCCC (20) mm mmCFP (8) mm mmUC284xSOIC (8) mm mmSOIC (14) mm mmPDIP (8) mm mmUC384xSOIC (8) mm mmSOIC (14) mm mmPDIP (8) mm mmCFP (8) mm mm(1)

4 For all available packages, see the orderable addendum at the end of the 2016, Texas Instruments IncorporatedSimplified ApplicationUC1842, UC2842, UC3842, UC1843, UC2843, UC3843UC1844, UC2844, UC3844, UC1845, UC2845, UC3845 SLUS223G APRIL 1997 REVISED JULY 2022An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION of Contents1 Revision Device Comparison Pin Configuration and Absolute Maximum ESD Recommended Operating Thermal Electrical Typical Detailed Functional Block Feature Device Functional Application and Application Typical Power Supply Layout Layout Device and Documentation Receiving Notification of Documentation Support Electrostatic Discharge Mechanical, Packaging, and Orderable Revision HistoryNOTE.

5 Page numbers for previous revisions may differ from page numbers in the current from Revision F (April 2020) to Revision G (July 2022)Page Updated the numbering format for tables, figures and cross-references throughout the from Revision E (January 2017) to Revision F (April 2020)Page Changed UVLO Table updated ..7UC1842, UC2842, UC3842, UC1843, UC2843, UC3843UC1844, UC2844, UC3844, UC1845, UC2845, UC3845 SLUS223G APRIL 1997 REVISED JULY Document FeedbackCopyright 2022 Texas Instruments IncorporatedProduct Folder Links: UC1842 UC2842 UC3842 UC1843 UC2843 UC3843 UC1844 UC2844 UC3844 UC1845 UC2845 UC38455 Device Comparison TableUVLOTEMPERATURE RANGEMAX DUTY CYCLETURNON AT 16 VTURNOFF AT 10 VSUITABLE FOR OFF-LINE APPLICATIONSTURNON AT VTURNOFF AT VSUITABLE FOR DC-DC APPLICATIONSUC1842UC1843 55 C to 125 CUp to 100%UC2842UC2843 40 C to 85 CUC3842UC38430 C to 70 CUC1844UC1845 55 C to 125 CUp to 50%UC2844UC2845 40 C to 85 CUC3844UC38450 C to 70 C6 Pin Configuration and FunctionsOUTPUTVCCVREFGROUNDVFBCOMPISENS ERT/CT12348765 Figure 6-1.

6 D, JG, and P Packages 8-Pin SOIC, CDIP, and PDIP Top View 1234567141312111098 VCCVCPWRGNDCOMPNCVFBNCISENSENCRT/CTGROUN DOUTPUTVREFNCF igure 6-2. D and W Packages 14-Pin SOIC and CFP Top View 9 10 11 12 133 2 1 20 19181716151445678 VCCVCNCOUTPUTNCNCVFBNCISENSENCNCRT/CTNCP WRGNDGROUNDNCCOMPNCVREFNCF igure 6-3. FK Package 20-Pin LCCC Top View Table 6-1. Pin FunctionsPINTYPEDESCRIPTIONNAMESOIC, CDIP, PDIP(8)SOIC, CFP(14)LCCC(20)COMP112 OError amplifier compensation pin. Connect external compensation components to this pin to modify the error amplifier output.

7 The error amplifier is internally current-limited so the user can command zero duty cycle by externally forcing COMP to , UC2842, UC3842, UC1843, UC2843, UC3843UC1844, UC2844, UC3844, UC1845, UC2845, UC3845 SLUS223G APRIL 1997 REVISED JULY 2022 Copyright 2022 Texas Instruments IncorporatedSubmit Document Feedback3 Product Folder Links: UC1842 UC2842 UC3842 UC1843 UC2843 UC3843 UC1844 UC2844 UC3844 UC1845 UC2845 UC3845 Table 6-1. Pin Functions (continued)PINTYPEDESCRIPTIONNAMESOIC, CDIP, PDIP(8)SOIC, CFP(14)LCCC(20)GROUND5913 GAnalog ground. For device packages without PWRGND, GROUND functions as both power ground and analog 812 GPower ground.

8 For device packages without PWRGND, GROUND functions as both power ground and analog groundISENSE357 IPrimary-side current sense pin. Connect to current sensing resistor. The PWM uses this signal to terminate the OUTPUT switch conduction. A voltage ramp can be applied to this pin to run the device with a voltage-mode control 2, 4, 6, 131, 3, 4, 6, 8, 9, 11, 14, 16, 19 Do not connectOUTPUT61015 OOUTPUT is the gate drive for the external MOSFET. OUTPUT is the output of the on-chip driver stage intended to directly drive a MOSFET. Peak currents of up to 1 A are sourced and sunk by this pin.

9 OUTPUT is actively held low when VCC is below the turnon frequency oscillator set point. Connect timing resistor, RRT, to VREF and timing capacitor, CCT, to GROUND from this pin to set the switching frequency. For best performance, keep the timing capacitor lead to the device GROUND as short and direct as possible. If possible, use separate ground traces for the timing capacitor and all other frequency of the oscillator can be estimated with the following equations:fOSC= CCT (1)where fOSC is in Hertz, RRT is in Ohms and CCT is in Farads. Never use a timing resistor less than 5 k.

10 The frequency of the OUTPUT gate drive of the UCx842 and UCx843, fSW, is equal to fOSC at up to 100% duty cycle; the frequency of the UCx844 and UCx845 is equal to half of the fOSC frequency at up to 50% duty 1117 IBias supply input for the output gate drive. For PWM Controllers that do not have this pin, the gate driver is biased from the VCC pin. VC must have a bypass capacitor at least 10 times greater than the gate capacitance of the main switching FET used in the controller bias input that provides power to the device. Total VCC current is the sum of the quiescent VCC current and the average OUTPUT current.


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