Understanding High-Speed Signals, Clocks, and …

1 ADC08D1000,ADC08D1500,ADC10DL065,ADC12DL 040,ADC12DL065,ADC12QS065,LMH6550,LMH655 1,LMH6703 Understanding High-Speed Signals, Clocks, and Data CaptureLiterature Number: SNAA121 Feature Imaging and MeasurementSolution ..4-5 Design PATH designerSMTips, tricks, and techniques from the analog signal -path expertsAs today s data conversion sample rates for analog-to-digital converters are moving into the Giga Samples Per Second (GSPS) range, systems need to be capable of such high conversion rates and the supportinganalog components have to generate and amplify high -frequency signals.

2 Inaddition to the analog signal path, the circuit areas that the designer shouldthoroughly understand are the sampling clock and the capturing of digital dataat high bit rates. This issue of the signal Path Designerwill provide suggestedsolutions for these two key areas. The following information is particularly relevant for systems that require high -performance Sources One of the most important sub-circuits within a High-Speed data conversionsystem is the clock source.

3 This is because the timing accuracy of the clock sig-nal can directly affect the dynamic performance of the ADC. To minimize thisinfluence, an ADC clock source must exhibit very low levels of timing jitter orphase noise. If this factor is not considered when choosing a clock circuit, thesystem could deliver poor dynamic performance irrespective of the quality ofthe front-end analog input circuitry or ADC. A perfect clock will always deliver edge transitions at precise time intervals. In practice, clock edges willarrive at continuously varying intervals.

4 As a result of this timing uncertainty, Understanding High-Speed Signals, Clocks, and Data capture By Ian King, Applications EngineerNo. 103 NEXT ISSUE: Precision Sensor InterfacePoor ClockFrequency SpectrumGood ClockFrequency SpectrumFrequencyFrequencyAmplitudeAmpli tudeFigure 1. Examples of clock signal Spectral Analysis8203_Signal_Path_103 10/17/05 14:52 Page 1 high -Performance Solutions for Medical ImagingSimplified Positron-Emission Tomography (PET) Scanner Block DiagramVGAsQuad AmpQuad ADCP hotoMultiplierOutputsScintillationCrysta lsSummingAmpComparatorFPGAP roduct IDTypeSSBW (MHz, Av= 1)Slew Rate(V/ s, Av=1)ICC(mA/ch)2nd/3rd HD (dBc, VOUT= 2 VPP)Voltage Noise(nV/ Hz)

5 PackageLMH6550 Fully differential ADC driver w/ / -103 at 5 MHz, RL=800 , MSOP-8 LMH6551 Fully differential ADC / -96 at 5 MHz, RL=800 , GHz low distortion op amp / -90 at 20 MHz, RL=100 , SOT23-6 LMH6502 Linear in dB, variable gain / -57 at 20 MHz, RL=100 , TSSOP-14 LMH6503 Linear in V/V, variable gain / -61 at 20 MHz, RL=100 , TSSOP-14 LMH6504 Linear in dB, variable gain / -55 at 20 MHz, RL=100 , MSOP-8 LMH6722 Quad wideband, low power op / -85 at 5 MHz, RL=100 , ultra low power op / -63 at 5 MHz, RL=100 , TSSOP-14 Product IDTypeResponse Time (ns)Rise/Fall TimesICC(mA/ch)CMVRO utput ConfigPackageLMV72197 ns, to 5V comparator w/ to , SOT23-5 NEW!

6 NEW!NEW!21Av= +102Av= +2 High-Speed Amplifiers and Comparators for Medical ImagingProduct IDResolutionSpeed(MSPS)Supply Voltage (V)Power (mW)SFDR (dB)THD (dB)ENOB (bit)SNR (dB)PackageADC1006510 59 TSSOP-28 ADC1008010 61 TQFP-64 ADC12DL04012-bit , LLP-60 ADC14L020 14 ADCs for Medical ImagingDynamic PerformanceNEW!NEW!NEW!8203_Signal_Path_ 103 10/17/05 14:52 Page 2the signal -to-noise ratio of a sampled waveform canbe compromised by the data conversion maximum clock jitter that can be tolerated fromall jitter sources before the noise due to jitter exceedsthe quantization noise (1/2 LSB).

7 This is definedfrom the following equation: Tj(rms)= (VIN(p-p)/ VINFSR) x (1/(2(N+1)x x fin))If the Input Voltage (VIN) is optimized to equal thefull scale range of the ADC (VINFSR), then the jit-ter requirement becomes a factor of the ADC s res-olution (N bits) and the input frequency beingsampled (fin).For input frequencies up to the Nyquist rate (500 MHz for a 1 GSPS conversion rate), the totaljitter requirement would be: Tj(rms)= 1 x (1/(2(8+1)x x 500 x 106))Tj(rms)= psThis value represents the total jitter from allsources.

8 A source of jitter that can be accounted forwithin the ADC device itself is called the aperturejitter. This is a timing uncertainty associated withthe input sample and hold circuit of the device andshould be considered when determining the maxi-mum allowable clock jitter of the clock source. clock Circuit Jitter = SQRT (Tj(rms)2 (ADC Aperture Jitter)2)Using the ADC08D1000 as an example, the aperture jitter is given in the datasheet as ps,this value tightens the jitter specification for theADC clock to ~ ps.

9 However, simply matching an oscillator s perform-ance data to the requirements specification may notbe enough to obtain the expected result when usedin the data conversion system. This is because frequency components that exist alongside the fundamental also play a significant role. It is there-fore important to examine the clock signal with aspectrum analyzer and make sure that the energyassociated with the fundamental frequency is notspread over too wide a range.

10 Spurs that extend tohigher frequencies may be visible and will also havea direct impact on jitter performance. Figure 1 compares an example of a poor performance clocksignal alongside the frequency spectrum that wouldbe expected from a good, clean low-jitter 2shows the recommended clock circuit forthe ADC08D1000. It consists of a Phase LockedLoop (PLL) device (LMX2312) connected to aVari-L Voltage Controlled Oscillator (VCO). The PLL and VCO maintains the required signalto noise ratio (46 dB) for the ADC08D1000 product up to the Nyquist input frequency.