WLCSP (FI - STATS ChipPAC Ltd

1 LEVEL chip scale PACKAGINGW afer Level chip scale Package ( WLCSP ) offers one of the most compact package footprints, providing increased functionality, improved thermal performance and finer pitch interconnection to the printed circuit board. With WLCSP , all of the manufacturing process steps are performed in parallel at the silicon wafer level rather than sequentially on individual chips to achieve a package that is essentially the same size as the die. The resultant package has dielectrics, thin film metals, and solder bumps directly on the surface of the die with no additional packaging . The basic structure of the WLCSP has an active surface with polymer coatings and bumps with bare silicon exposed on the remaining sides and back of the die. Breakthrough FlexLine wafer Level ManufacturingSTATS ChipPAC s innovative approach to WLCSP manufacturing, known as the FlexLine method, provides customers freedom from wafer diameter constraints, while enabling supply chain simplification and significant cost reductions that are not possible with a conventional manufacturing flow.

2 This FlexLine manufacturing method delivers an unmatched level of flexibility and cost savings for fan-in and fan-out wafer level Quality, Lower Costs: eWLCSP The encapsulation material that is a part of the FlexLine manufacturing process has enabled an innovative WLCSP packaging technology called encapsulated wafer Level chip scale Package (eWLCSP ). An intrinsic feature of eWLCSP is the thin polymer casing formed on the back and four sidewalls of the die, providing mechanical robustness and resistance to chipping, cracking and handling damage, as well as improved long term reliability compared to traditional bare die WLCSP . eWLCSP provides a measurable increase in overall component strength of more than 50% over traditional WLCSP structures. The combined benefits of superior quality, lower cost structure and the ease of conversion through a drop-in replacement make eWLCSP a compelling value 200mm & 300mm wafer bumping offers advanced technology in WLP services that enable higher current densities & increased reliability Repassivation, Redistribution, Bumping and IPD layer options available Full turnkey wafer bumping & Flip chip -in-Package assembly capabilityWafer Level chip scale PackageWLCSP (FIWLP Technology) STATS ChipPAC offers high performance fan-in wafer level packaging (FIWLP)

3 Solutions that provide significant package footprint reductions, lower cost, improved electrical performance, and a relatively simpler construction over conventional wirebond or interposer packaging WLCSP body sizes qualified up to 6x6mm Ball count ranges depending on pitch size and up to 300 Die services available for 8 -12 wafers In-house thin film on wafer processing & bumping Full service wafer bumping with Polyimide or PBO dielectric options for wafer repassivation, redistribution and IPD layers Bumps formed by printed paste, electroplate or ball drop solder bump technologies Minimum available flip chip bump pitch of 150 m Large bump (220-500 m) processing at pitch & greater for Flip chip -on-Board & WLCSP applications For larger pitch applications, either printed paste bumping or mechanical ball drop available Eutectic and Pb-free solder Copper under bump metallization (UBM) & redistribution layers (RDL) available wafer level IPD & thick copper (8-12 m) conductors available Underfilling of substrate mounted bumped die may or may not be required depending on customer s specific application & reli-ability requirements Underfilling by overmolding is feasible Low cure temperature polymers available Flexible bare die processing Compatible with conventional SMT assembly and test techniques APPLICATIONSA small, lightweight, high performance semiconductor solution, WLCSP is a compelling, cost effective solution for space constrained mobile applications and other portable consumer and industrial devices.

4 Copyright 2014. STATS ChipPAC Ltd. All rights 2014 The STATS ChipPAC logo is a registered trademark of STATS ChipPAC Ltd. Trademark registered in United States. Singapore company registration number 199407932D. All other product names and other company names herein are for identification purposes only and may be the trademarks or registered trademarks of their respective owners. STATS ChipPAC disclaims any and all rights in those marks. STATS ChipPAC makes no guarantee or warranty of its accuracy in the information given, or that the use of such information will not infringe on intellectual rights of third parties. Under no circumstances shall STATS ChipPAC be liable for any damages whatsoever arising out of the use of, or inability to use the materials in this document. STATS ChipPAC reserves the right to change the information at any time and without notice. Corporate Office 10 Ang Mo Kio St. 65, #05-17/20 Techpoint, Singapore 569059 Tel: 65-6824-7777 Fax: 65-6720-7823 Global Offices USA 510-979-8000 CHINA 86-21-5976-5858 KOREA 82-31-639-8911 TAIWAN 886-3-593-6565 SWITZERLAND 41-22-929-5658 PROCESS HIGHLIGHTSDie Thickness 8 200-760 m (8-30mils) 12 250-790 m (10-32mils) Bumped Die Height minimum; and standardPrinted Bump Height 70 m Solder Sphere Diameter 250 m ball dropBump Pitch , , , 10 m lines, 10 m spacesVisual Inspection Automatic optical inspection with electronic wafer mappingSTANDARD MATERIALSD ielectric Material Polymide & PBORDL Sputtered AlCu, Plated CuUBM AlCu/NiV/Cu, Ti/NiV/Cu, Plated CuSolder Alloy Eutectic (standard and ultra-low alpha) including Pb-free SAC 405, 305 or 105 ( , or )Ball Hi Pb, Eutectic, Pb-free.

5 LF35 (available on request)Electroplate Hi Pb, Eutectic, Pb-free RELATED SERVICESW afer Thinning Fully automated backgrinding & mechanical polishingBackside Coating Laminated coatingMarking Laser marking Packing Options Fully automated die pick/place into custom pocket tape/reel or waffle pack mediaCOMPONENT LEVEL RELIABILITY TESTINGM oisture Sensitivity Level Eutectic printed bump: JEDEC Level 1 @ 220 C Pb-free printed bump: JEDEC Level 1 @ 260 CTemperature Cycling -55 C/125 C, 1000 cycles (eutectic & Pb-free printed bumps)High Temperature Storage 150 C, 1000 hrs (eutectic & Pb-free printed bumps)Multiple Solder Reflow 5x, 10x and 20x reflows with minimal reduction in bump shear strengthPressure Cooker Test 121 C/ 100% RH, 168 hrs THERMAL PERFORMANCE Thermal performance in the 20-40 C/W range for a 5mm x 5mm die without thermal enhancement Application specific thermal characterization available upon requestELECTRICAL PERFORMANCE Dependent on application design, and capable to beyond 10 GHz Application specific electrical characterization available upon request Thick Cu for high current low inductance applicationsWafer Level chip scale Package WLCSP (FIWLP Technology)(Not to scale )

6 TEST SERVICESW afer level testing is an important process for yield enhancement of flip chip packages and a final test requirement for WLCSPs. STATS ChipPAC s best-in-class test services include: Product Engineering support Probe capability Program generation/conversion High volume wafer sortFLEXLINE PROCESS FLOW CROSS-SECTIONSRPV (Repassivation)RDL 3M (Redistribution)FOC (Bump on I/O) 200mm onlyThick Copper RDL (12 m) 200mm onlyWLCSPeWLCSP WLCSP Bumped Bare DieSi wafer backgrindSi wafer dicingReconstitutionRedistributionBall drop / reflowPanel probeBackgrind (opt)Laser markingPkg singulationPkg pick & placeShip in TnRRDL 4M (Redistribution)UBMBumpRunnerBumpP2P1P1 UBMBumpUBMBumpRunnerP2P1PI-2 Plated Cu RDL/UBMPI-1 (optional)