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1 1 ixys reserves the right to change limits, test conditions and dimensionsContentsPageSymbols and Definitions2 Nomenclature2 General Informations for Chips3 Assembly Instructions4 FRED, Rectifier Diode and Thyristor Chips in Planar Design5 IGBT ChipsVCESICG-Series, Low VCE(sat) B2 Types600 ..1200 V7 .. 20 A6G-Series, Fast C2 Types600 V7 .. 20 A6S-Series, SCSOA Capability, Fast Types600 V10 .. 20 A6E-Series, Improved NPT technology1200 .. 1700 V20 .. 150 A7 MOSFET ChipsVDSSRDS(on)HiPerFETTM Power MOSFET70 ..1200 .. 8-10 PolarHT/HVTM Power MOSFET55 .. 600 .. 11 PolarHT/HVTM HiPerFET Power MOSFET100.

2 600 .. 12-14N-Channel Depletion Mode MOSFET500 ..1000 V30 .. 110 15P-Channel Power MOSFET-100 ..-600 .. 15 Chip outlines16-23 Bipolar ChipsVRRM / VDRMIF(AV)M / IT(AV)MRectifier Diodes800 .. 2200 V12 .. 788 A24-25 FREDs200 .. 1200 V8 .. 244 A26-28 Low Leakage FREDs200 .. 1200 V9 .. 148 A29-30 SONIC-FRDTM Diodes600 .. 1800 V12 .. 150 A31-32 GaAs Schottky Diodes100 .. 300 .. 25 A33-34 Schottky Diodes8 .. 200 V28 .. 145 A35-38 Phase Control Thyristors800 .. 2200 V15 .. 540 A39-40 Fast Rectifier Diodes1600 .. 1800 V10 .. 26 A41 Direct Copper Bonded (DCB) Ceramic SubstratesWhat is DCB?

3 42 DCB 2008 ixys All rights reservedRegistration No.:OHSAS 18001:001947 OHSymbols and Definitions CiesInput capacitance of IGBT CissInput capacitance of MOSFET -di/dtRate of decrease of forward current ICDC collector current IDDrain current IFForward current of diode IF(AV)MMaximum average forward current at specified Th IFSMPeak one cycle surge forward current IGTGate trigger current IRReverse current IRMM aximum peak recovery current ITForward current of thyristor IT(AV)MMaximum average on-state current of a thyristorat specified Th ITSMM aximum surge current of a thyristor RDS(on)

4 Static drain-source on-state resistance RthjcThermal resistance junction to case rTSlope resistance of a thyristor or diode(for power loss calculations) TcaseCase temperature ThHeatsink temperature tfiCurrent fall time with inductive load Tj, T(vj)Junction temperature Tjm, T(vj)mMaximum junction temperature trrReverse recovery time of a diode VCE(sat)Collector-emitter saturation voltage VCESM aximum collector-emitter voltage VDRMM aximum repetitive forward blockingvoltage of thyristor VDSSD rain-source break-down voltage VFForward voltage of diode VRReverse voltage VRRMM aximum peak reverse voltage of thyristor ordiode VTOn-state voltage of thyristor VT0 Threshold voltage of thyristors or diodes (forpower loss calculation only)

5 Chip and DCB Ceramic Substrates catalogueEdition 2008 Published by ixys Semiconductor GmbHMarketing CommunicationsEdisonstra e 15, D-68623 Lampertheim ixys Semiconductor GmbH All Rights reservedAs far as patents or other rights of third parties are concerned, liability is onlyassumed for chips and DCB parts per se, not for applications, processes andcircuits implemented with components or assemblies. Terms of delivery and theright to change design or specifications are and MOSFET DiscreteIXSD 40N60A(Example)IXIXYSDie technologyENPT3 IGBTFHiPerFETTM Power MOSFETGFast IGBTSIGBT with SCSOA capabilityTStandard Power MOSFETDU nassembled chip (die)40 Current rating, 40 = 40 ANN-channel typePP-channel type60 Voltage class, 60 = 600 VxxMOSFETAP rime RDS(on) for standard MOSFETQLow gate charge dieQ2 Low gate charge die, 2nd generationPPolarHT/HV Power MOSFETLL inear Mode MOSFETIGBT--No letter, low VCE(sat)

6 AOr A2, std speed typeBOr B2, high speed typeCOr C2, very high speed typeW-CWP 55-12/18(Thyristor Example)WPackage typeCChip functionC = Silicon phase control thyristorWUnassembled chipPProcess designatorP = Planar passivated chip cathode on top55 Current rating value of one chip in A12/18 Voltage class, 12/18 = 1200 up to 1800 VDiode and Thyristor ChipsC-DWEP 69-12(Diode Example)CPackage typeDChip functionD = Silicon rectifier diodeWUnassembled chipEPProcess designatorEP = Epitaxial rectifier diodeN = Rectifier diode, cathode on topP = Rectifier diode, anode on topFN = Fast Rectifier diode, cathode on topFP = Fast Rectifier diode, anode on top69 Current rating value of one chip in A-12 Voltage class, 12 = 1200 VRegistration No.

7 :ISO/TS 16949:001947 TS2 Registration No.:ISO 14001:001947 UM3 ixys reserves the right to change limits, test conditions and dimensions General Informations for ChipsWhen mounting Power Semiconductor chips to a header, ceramic substrate or hybrid thick film circuit, the solder system and the chipattach process are very important to the reliability and performance of the final product. This brochure provides several guidelinesthat describe recommended chip attachment procedures. These methods have been used successfully for many years at Packaging OptionsIXYS offers various order from one of the following possibilities:Packaging OptionsDelivery *Chips in tray (Waffle Pack);Electrically *Chips in wafer, unsawed;Bipolar = 5" (125 mm ) wafer;or 6 " (150 mm ) *Chips in wafer on foil, sawed;Bipolar = 5" (125 mm ) wafer;or 6 " (150 mm ).

8 * must be amended by the exact chip type , Storage and HandlingChips should be transported in their original containers. All chip transfer to other containers or for assembly should be done only withrubber-tipped vacuum pencils. Contact with human skin (or with a tool that has been touched by hand) leaves an oily residue that mayadversely impact subsequent chip attach or temperatures below 104 F (40 C), there is no limitation on storage time for chips in sealed original packages. Chips removed fromoriginal packages should be assembled immediately. The wetting ability of the contact metallization with solder can be preserved bystorage in a clean and dry nitrogen IGBT and MOSFET Chips are electrostatic discharge (ESD) sensitive.

9 Normal ESD precautions for handling must be to chip attach, all testing and handling of the chips must be done at ESD safe work stations according to DIN IEC 47(CO) air blowers are recommended for added ESD of the chips degrades the assembly prints, dust or oily deposits on the surface of the chips have to beabsolutely mechanical treatment can cause damage to the TestsThe electrical properties listed in the data sheet presume correctly assembled chips. Testing of non-assembled chips requires thefollowing precautions: High currents have to be supplied homogeneously to the whole metallized contact area.

10 Kelvin probes must be used to test voltages at high currents Applying the full specified blocking or reverse voltage may cause arcing across the glass passivated junction termination,because the electrical field on top of the passivation glass causes ionization of the surrounding air. This phenomenon can beavoided by using inert fluids or by increasing the pressure of the gas surrounding the chip to values above 30 psig (2 bars).General Rules for AssemblyThe linear thermal expansion coefficient of silicon is very small compared to usual contact metals. If a large area metallized siliconchip is directly soldered to a metal like copper, enormous shear stress is caused by temperature changes ( when cooling down fromthe solder temperature or by heating during working conditions) which can disrupt the solder it is found that larger chips are cracking during mountdown or in the application, then the use of a low thermal expansion coefficientbuffer layer, tungsten, molybdenum or Trimetal , for strain relief should be considered.