www.ti.com SLES197C– APRIL 2007– REVISED …

1 APRIL2007 REVISEDMARCH2011 DigitalAudioProcessor FullyProgrammableWiththeGraphical,Drag-a nd-DropPurePathStudio SoftwareDevelopmentEnvironment 135-MHzOperation 48-BitDataPathWith76-BitAccumulator HardwareSingle-CycleMultiplier(28 48) FiveSimultaneousOperationsPerClockCycle Usable768 WordsDataRAM(48 Bit),Usable1kCoefficientRAM(28 Bit) 122msat48kHz, MasterModeFsis48kHz AnalogAudioInput/Output Two3:1 StereoAnalogInputMUXes FourDifferentialADCs(102dBDNR,Typical) FourDifferentialDACs(105dBDNR,Typical) DigitalAudioInput/Output TwoSynchronousSerialAudioInputs(FourChan nels) TwoSynchronousSerialAudioOutputs(FourCha nnels) InputandOutputDataFormats.

2 16-,20-,or24-BitDataLeft,Right,andI2S SystemControlProcessor Embedded8051 WARPM icroprocessor ProgrammableUsingStandard8051C Compilers UptoFourProgrammableGPIOPins GeneralFeatures TwoI2C PortsforSlaveorMasterDownload MP3 Player/MusicPhoneDocks SpeakerBars Mini/Micro-ComponentSystems MusicalInstruments SpeakerEqualization StudioMonitors1 Pleasebeawarethatanimportantnoticeconcer ningavailability,standardwarranty,anduse in a 2007 2011, APRIL2007 a highly-integratedaudiosystem-on-chip(SOC )consistingofa fully-programmable,48-bitdigitalaudiopro cessor,a3:1stereoanaloginputMUX,fourADCs ,fourDACs, highlyintuitive,drag-and-dropenvironment thatminimizessoftwaredevelopmenteffortwh ileallowingtheendusertoutilizethepoweran dflexibilityoftheTAS3204 s ,volume/bass/treblecontrol,signalmixing/ MUXing/splitting,delaycompensation,dynam icrangecompression, ,stereowidening, custom-designed,fully-programmable135-MH z, , digitalaudioprocessing2 IntroductionCopyright 2007 2011,TexasInstrumentsIncorporatedSubmitD ocumentationFeedbackProductFolderLink(s) .

3 tas3204 DSP Core8051 Microprocessor CoreOscillatorDPLLC lockDivider512Fs XTALMCLK_IN512 FsSlaveMasterClockGenerationSerial Audio PortLRCLK_OUTSCLK_OUTLRCLK_INSCLK_INSDOU T1/2 Two StereoADCT hreeDifferentialStereoAnalog InputsTwo StereoDACTwo DifferentialStereo AnalogOutputsSCL1/SDA1 SCL2/SDA2 GPIO1/2 Master/Slave256 FsPowerSupplyAVDDDVDD128 FsVolumeUpdateInputCrossBarMixerOutput CrossBar MixerSDIN1/2 ClocksLegendDigital DataAnalog DataInternal ConnectionExternal ConnectionControlRegistersExternalRAM 2 KCodeRAM 16K8-BitMCUI nternalRAM 256 Data RAM1K Upper Mem768 Lower APRIL2007 (PN)(1)(2)0 C to70 CTAS3204 PAG(1)Packagedrawings,thermaldata, (2)Forthemostcurrentpackageandorderingin formation,seethePackageOptionAddendumatt heendofthisdocument, 2007 2011,TexasInstrumentsIncorporatedIntrodu ction3 SubmitDocumentationFeedbackProductFolder Link(s): tas3204 tas3204 SLES197C APRIL2007 , ( tas3204 ) (SAP).

4 11I/ (0x00).. (0x02).. MemoryLoadControlandDataRegisters( ).. (0x06and0x07).. (0x08).. (0x10and0x11).. (0x12)..558I2C (0x13).. (0x14,0x15,0x17,0x18) (0x1A,0x1B,0x1D).. (0x1E).. (RESET)- (0x1F).. (VREG_EN).. (0x21and0x22).. (PDN).. (0x30to0x3F).. BusControl(CS0).. (ESFR) (GPIO).. 2007 2011,TexasInstrumentsIncorporatedSubmitD ocumentationFeedbackProductFolderLink(s) : tas3204 SDOUT1 SDOUT2 DifferentialAnalogOutSDIN1 SDIN2 DifferentialAnalogInMCLK_INLRCLK_INSCLK_ INMCLK_OUTxLRCLK_OUTSCLK_OUTI2C Port #1I2C Port #2 OutputSAPS tereoDACS tereoDACV olumeUpdateInputSAPS tereoADCS tereoADCPLLandClockControlTAS3204I2 CInterfaceDigital AudioProcessor Core48-Bit Data Path28-Bit Coefficients76-Bit MAC3K Code RAM1K Upper Data RAM768 Lower Data Coeff.

5 RAMBoot ROM8051 MCU8-Bit Microprocessor256 IRAM2K ERAM16K Code RAM10K Code ROM22232222422422 PAG PACKAGE(TOP VIEW)12345678910111213141516484746454443 4241403938373635343317181920212223242526 2728293031326463626160595857565554535251 5049I2C1_SCLI2C1_SDAGPIO2 GPIO1 MUTECS0 PDNDVSS1 DVDD1VR_PLLAVSSIAIN1 LPAIN1 LMAIN1 RPAIN1 RMAIN2 LPAIN2 LMAIN2 RPAIN2 RMAIN3 LPAIN3 LMAIN3 RPAIN3 RMAVDD1 VMIDVREFREXTAVDD2 AOUT2 LMAOUT2 LPAOUT2 RMAOUT2 RPMCLK_OUT1 MCLK_OUT2 MCLK_OUT3 DVDD2 DVSS2 MCLK_INXTAL_OUTXTAL_INAVDD3VR_ANAAVSS_ES DAVSSOAOUT1 RPAOUT1 RMAOUT1 LPAOUT1 LMI2C2_SCLI2C2_SDARESETSDIN1/GPIO3 SDIN2 APRIL2007 2007 2011,TexasInstrumentsIncorporatedPhysica lCharacteristics5 SubmitDocumentationFeedbackProductFolder Link(s).

6 tas3204 tas3204 SLES197C APRIL2007 (1)PULLDOWN(2) (3)Analogchannel1 leftnegativeinputAIN1LP12 AnalogInputAnalogchannel1 leftpositiveinputAIN1RM15 AnalogInputPulltoVMID(3)Analogchannel1ri ghtnegativeinputAIN1RP14 AnalogInputAnalogchannel1 rightpositiveinputAIN2LM17 AnalogInputPulltoVMID(3)Analogchannel2 leftnegativeinputAIN2LP16 AnalogInputAnalogchannel2 leftpositiveinputAIN2RM19 AnalogInputPulltoVMID(3)Analogchannel2 rightnegativeinputAIN2RP18 AnalogInputAnalogchannel2 rightpositiveinputAIN3LM21 AnalogInputPulltoVMID(3)Analogchannel3 leftnegativeinputAIN3LP20 AnalogInputAnalogchannel3 leftpositiveinputAIN3RM23 AnalogInputPulltoVMID(3)

7 Analogchannel3 rightnegativeinputAIN3RP22 AnalogInputAnalogchannel3 rightpositiveinputAOUT1LM33 AnalogOutputAnalogchannel1 leftnegativeoutputAOUT1LP34 AnalogOutputAnalogchannel1 leftpositiveoutputAOUT1RM35 AnalogOutputAnalogchannel1 rightnegativeoutputAOUT1RP36 AnalogOutputAnalogchannel1 rightpositiveoutputAOUT2LM29 AnalogOutputAnalogchannel2 leftnegativeoutputAOUT2LP30 AnalogOutputAnalogchannel2 leftpositiveoutputAOUT2RM31 AnalogOutputAnalogchannel2 rightnegativeoutputAOUT2RP32 AnalogOutputAnalogchannel2 # #2I2C1_SCL1 DigitalInputSlaveI2C serialcontroldatainterfaceinput/output.( 1)I = input;O = output(2)Allpullupsare20- Aweakpullups,andallpulldownsare20- theterminalsareleftunconnected(pullups logic1 input;pulldowns logic0 input).

8 Devicesthatdriveinputswithpullupsmustbea bletosink20 A whilemaintaininga A whilemaintaininga logic-1drivelevel.(3)PulltoVMID whenanaloginputis in 2007 2011,TexasInstrumentsIncorporatedSubmitD ocumentationFeedbackProductFolderLink(s) APRIL2007 REVISEDMARCH2011 TERMINALINPUT/PULLUP/DESCRIPTIONOUTPUT(1 )PULLDOWN(2) (frame)clockinputforI2S interfaceLRCLK_OUT51 DigitalOutputLeft/right(frame)clockoutpu tforI2S interfaceMCLK_IN43 DigitalInputPulldownMasterclockinputforI 2S 512x FsMCLK_OUT148 DigitalOutputMasterclockoutputforI2S interfaceFrequency= 256x FsMCLK_OUT247 DigitalOutputProgrammablemasterclockoutp utdividerMCLK_OUT346 DigitalOutputProgrammablemasterclockoutp utdividerThispinneedstobeprogrammedasmut epinin ,itsfunctionis 22k (1%tolerance) (bit)clockinputforI2S interfaceSCLK_OUT52 DigitalOutputSerial(bit)

9 ClockoutputforI2S interfaceSDIN1/GPIO361 DigitalI/OPullupSerialdatainput#1forI2S interface/ generalpurposeinput/output#3 SDIN2/GPIO460 DigitalI/OPullupSerialdatainput#2forI2S interface/ generalpurposeinput/output#4 SDOUT154 DigitalOutputSerialdataoutput#1forI2S interfaceSDOUT253 DigitalOutputSerialdataoutput#2forI2S FVMID25 AnalogOutputlow-ESRcapacitorandanexterna l10- F filtercap.(4) F lowESRcapacitoranda F (4) F lowESRcapacitoranda F (4) F low-ESRcapacitoranda F (4) F (4) 512x 512x Fs(4)If desired, 2007 2011,TexasInstrumentsIncorporatedPhysica lCharacteristics7 SubmitDocumentationFeedbackProductFolder Link(s): tas3204 DPLL 4135-MHz DCLKM icroprocessor ClockMCLK_OUTMCLK_OUT2 MCLK_OUT3 ProgrammableDivider 2 2 2 64 2 ProgrammableDividerMaster/SlaveLRCLK_OUT SCLK_OUTSDOUTTo DAPP arallelDataSDINFrom DAPP arallelDataLRCLKRe-CreationSerialAudio PortReceiverSerialAudio MHzTAS3204 SLES197C APRIL2007.

10 CoreClockmanagement Overseestheselectionoftheclockfrequencie sforthe8051 MCU,theI2C controller,andtheaudioDSPcore Themasterclock(MCLK_INorXTAL_IN)is thesourcefortheseclocks. Inmostapplications,themasterclockdrivesa non-chipdigitalphase-lockedloop(DPLL),an dtheDPLL outputdrivestheMCUandaudioDSPclocks. DPLL bypassmodeis alsoavailable,in whichthehigh-speedmasterclockdirectlydri vestheMCUandaudioDSPclocks. SerialAudioPort(SAP)clockmanagement OverseesSAPmaster/slavemode ControlsoutputofSCLKOUT,andLRCLKin theSAPmastermodeFigure3-1showsa ,MCU, DSPclockoperatesata fixedfrequencyof2816x Fs MCUclockoperatesata fixedfrequencyof704x Fs.