Set-Reset (SR) Latch

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C. E. Stroud, Dept. of ECE, Auburn of a Flip-FlopELEC 4200Set-Reset (SR) LatchAsynchronousLevel sensitivecross-coupled Nor gatesactive high inputs (only one can be active)cross-coupled Nand gatesactive low inputs (only one can be active)SRQ+Q+Function00QQStorage State01 0 1Reset10 1 0Set110-?0-?Indeterminate StateSRQ+Q+Function001-?1-?Indeterminate State01 1 0Set10 0 1Reset11QQStorage StateSRQQSRQQC. E. Stroud, Dept. of ECE, Auburn of a Flip-FlopELEC 4200Enabled Set-Reset (SR) LatchAsynchronousLevel sensitivecross-coupled Nor gatesactive high inputs (S & R cannot be active)cross-coupled Nand gatesactive low inputs (S & R cannot be active)ESRQ+Q+Function0xxQQStorage State100QQStorage State101 0 1Reset110 1 0Set1110-?0-?Indeterminate StateESRQ+Q+Function0001-?1-?Indetermina te State001 1 0Set010 0 1Reset011QQStorage State1xxQQStorage StateSRQQESRQQEC.

Asynchronous interfaces lead to metastability (minimize the async interface & double clock data to reduce probability of metastability) Avoid asynchronous presets & clears on FFs (use sync presets & clears whenever possible) DO NOT construct a FF from two level sensitive latches of the same type with an inverter on the clock input to one latch

  Metastability