ASIC Physical Design Standard-Cell Design Flow

ASIC Physical DesignStandard-Cell Design FlowUsing the Cadence InnovusDigital Implementation SystemASIC Physical Design (Standard Cell)(can also do full custom layout)FloorplanChip/BlockPlace & RouteStd. CellsComponent-Level verilog NetlistIC Mask DataDesign RuleCheckStd. CellLayoutsCadence Innovus Digital Implementation SystemADiT/Eldo Simulation ModelBackannotateSchematicGenerateMask DataLayout RulesProcess DataLibrariesCalibreCalibreCalibreNetlis t-to-layoutdesign flowSynopsys JupiterXT Cadence SOC Innovus InnovusDigital Implementation (EDI) System GUIEDI Design flowFloorplan ( flat ) through implementationDesign Import (specify input files)File > Design ImportGate-level netlist verilog file(s) Physical data (LEF)Technology CellsIO pin planningPower planningTiming data andconstraintsExecutes init_designcommand to load files verilog gate-level netlist(s)

Verilog gate-level netlist(s) Gates from the standard cell library Design can be hierarchical or flat Tcl commands: set design_netlisttype verilog set init_verilog [list file1.v file2.v] set init_design_set_top 1. set init_top_cell“top” 0 to auto-assign top cell. specify if above = 1

Loading..

Tags:

  Verilog

Information

Related search queries