Transcription of ASIC Physical Design Standard-Cell Design Flow
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ASIC Physical Design Standard-Cell Design Flow
ASIC Physical DesignStandard-Cell Design FlowUsing the Cadence InnovusDigital Implementation SystemASIC Physical Design (Standard Cell)(can also do full custom layout)FloorplanChip/BlockPlace & RouteStd. CellsComponent-Level Verilog NetlistIC Mask DataDesign RuleCheckStd. CellLayoutsCadence Innovus Digital Implementation SystemADiT/Eldo Simulation ModelBackannotateSchematicGenerateMask DataLayout RulesProcess DataLibrariesCalibreCalibreCalibreNetlis t-to-layoutdesign flowSynopsys JupiterXT Cadence SOC Innovus InnovusDigital Implementation (EDI) System GUIEDI Design flowFloorplan ( flat ) through implementationDesign Import (specify input files)File > Design ImportGate-level netlist Verilog file(s) Physical data (LEF)Technology CellsIO pin planningPower planning
Design can be hierarchical or flat Tcl commands: set design_netlisttype verilog set init_verilog [list file1.v file2.v] set init_design_set_top 1. set init_top_cell“top” 0 to …
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