Transcription of CMOS Comparator Design
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CMOS Comparator Design
Department of Electrical and Computer Engineering Vishal Saxena -1- cmos Comparator Design Extra Slides Vishal Saxena, Boise State University Vishal Saxena -2- Comparator Design Considerations Comparator = Preamp (optional) + Reference Subtraction (optional for single-bit case) + Regenerative Latch +Static Latch to hold outputs (optional) Design Considerations Accuracy (dynamic and static offset, noise, resolution) Settling time (tracking BW, regeneration speed) Sensitivity/resolution (gain) Metastability (ability to make correct decisions) Overdrive recovery (memory) Power consumption Vishal Saxena -3- An Example cmos Comparator Vos orginiates from: Preamp input pair mismatch (Vth,W/L) PMOS loads and current mirror Latch offset Charge-Injection clock-feedthru imbalance of the reset switch (M9) Clock routing Parasitics M1M2 ViVosM3M4 VDDM5M6M8M7M9 VSS Vo+Vo-PreampLatch Vishal Saxena -4- Latch Regeneration Exponential regeneratio
CMOS Comparator Design Extra Slides ... Autozeroing techniques for offset storage and reduction ... “An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm2,” JSSC, vol. 32, pp. 1887-1895, issue 12, 1997. M 1 M 2 M 7 M 3 M 4 V i + V i-V o + V o-M 5 M 6 V id g m1 V id r o1 1 g m3 r o3-1 g m5 r o5 V od 3 g r //r //r //r g 1 // g 1 DM gain : A g m1 ...
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