CMOS Comparator Design

1 Department of Electrical and Computer Engineering Vishal Saxena -1- cmos Comparator Design Extra Slides Vishal Saxena, Boise State University Vishal Saxena -2- Comparator Design Considerations Comparator = Preamp (optional) + Reference Subtraction (optional for single-bit case) + Regenerative Latch +Static Latch to hold outputs (optional) Design Considerations Accuracy (dynamic and static offset, noise, resolution) Settling time (tracking BW, regeneration speed) Sensitivity/resolution (gain) Metastability (ability to make correct decisions) Overdrive recovery (memory) Power consumption Vishal Saxena -3- An Example cmos Comparator Vos orginiates from.

2 Preamp input pair mismatch (Vth,W/L) PMOS loads and current mirror Latch offset Charge-Injection clock-feedthru imbalance of the reset switch (M9) Clock routing Parasitics M1M2 ViVosM3M4 VDDM5M6M8M7M9 VSS Vo+Vo-PreampLatch Vishal Saxena -4- Latch Regeneration Exponential regeneration due to positive feedback of M7 and M8 VDDVSSVo PA tracking Latch resetingLatchregenratingVo+Vo-VDDM5M6M8M 7M9 VSS Vo+Vo-CLCL Vishal Saxena -5- Regeneration Speed Linear Model M8M7 CLCLVo+Vo-Vo-Vo+CLgmVo--1 Lmoo/Cgtexp0tV0tV pole RHP single ,/Cgs01/sCgs LmpLm 0VV/sCg111/sCVgVVVooLmLomooo Vishal Saxena -6- Reg. Speed Linear Model 0tVtVlngCtoomLM8M7 CLCLVo+Vo-Vo = 1 VVo(t=0)tVo Vo(t=0) t/(CL/gm) 1V 100mV 1V 10mV 1V 1mV 1V 100 V Vishal Saxena -7- Reg.

3 Speed Linear Model Reg. Speed Linear Model amplifier. be to g12R,Rg2 RgAm799m79m5V2 M5M6M8M7M9 =1Vo+Vo-Vm+Vm-M1M2 ViM3M4Vm+Vm-Vo+Vo-R92R92-1gm7-1gm7gm5Vm+ gm5Vm-X m3m1V1ggA V2V1iVioAA0VA0V0V LmV2V1io/CgtexpAA0 VtV x Vishal Saxena -8- Comparator Metastability Reg. Speed Linear Model LmV2V1io/CgtexpAA0 VtV Curve AV1AV2 Vi(t=0) 10 10 mV 10 1 mV 10 100 V 10 10 V Vo+ Vo-1234T/2 Comparator fails to produce valid logic outputs within T/2 when input falls into a region that is sufficiently close to the Comparator threshold Vishal Saxena -9- Comparator Metastability Reg. Speed Linear Model Cascade preamp stages (typical flash Comparator has 2-3 pre-amp stages) Use pipelined multi-stage latches; pre-amp can be pipelined too LSB1 BER LmV2V1io/CgtexpAA0 VtV ViDo jVosj+1 Assuming that the input is uniformly distributed over VFS, then Vishal Saxena -10- Charge-Injection and Clock-Feedthrough in Latch Reg.

4 Speed Linear Model M5M6M8M7 Vo+Vo-CLCLM9 CgdCgsVo+Vo- CM jump Charge injection (CI) and clock-feedthrough (CF) introduce CM jump in Vo+ and Vo- Dynamic latches are more susceptible to CI and CF errors Vishal Saxena -11- Dynamic Offset of a Latch Reg. Speed Linear Model Dynamic offset derives from: Imbalanced CI and CF Imbalanced load capacitance Mismatch b/t M7 and M8 Mismatch b/t M5 and M6 Clock routing Vo+Vo-offset50mV imbalance 10%jump Dynamic offset is usually the dominant offset error in latches Vishal Saxena -12- Typical cmos Comparator Reg. Speed Linear Model Input-referred latch offset gets divided by the gain of PA Preamp introduces its own offset (mostly static due to Vth, W, and L mismatches) PA also reduces kickback noise M1M2 ViVosM3M4 VDDM5M6M8M7M9 VSS Vo+Vo-PreampLatchKickback noise disturbs reference voltages, must settle before next sample Vishal Saxena -13- Comparator Offset Reg.

5 Speed Linear Model M1M2 ViVosM3M4 VDDM5M6M8M7M9 VSS Vo+Vo-PreampLatch LL 2222osthovW 1V V VW49m79m5V2Rg2 RgA m3m1V1ggA 2V22V12dynos,2V22V12os,782V12os,562os,34 2os,122osAAVAAVAVVVV Differential pair mismatch: Total input-referred Comparator offset: Vishal Saxena -14- Recall: Matching Properties Reg. Speed Linear Model ,DSWLA P 22P2P2 Suppose parameter P of two rectangular devices has a mismatch error of P. The variance of parameter P b/t the two devices is where, W and L are the effective width and length, D is the distance Ref: M. J. M. Pelgrom, et al., Matching properties of MOS transistors, IEEE Journal of Solid-State Circuits, vol. 24, pp.

6 1433-1439, issue 5, 1989. 2222 VththVth22 22 2 AThreshold : V =+ SDWLA Current factor : S D WL1st term dominates for small devices Vishal Saxena -15- Recall: Device Sizing for Mismatch Reg. Speed Linear Model 1SR1 LRR with std identical resistorsR1 R2 R2R1R1R211 10 111R10 RRR10 AWL j2S1R210222R2RR1R2R1j1 LRR 1010R with std ,W 10 10 Spatial averaging Vishal Saxena -16- Pre-amp Design A fully-differential gain-stage Avoid or use simple CMFB Pre-amp gain reduces input referred offset due to the latch Autozeroing techniques for offset storage and reduction Pre-amp open-loop gain vs tracking bandwidth trade-off Multiple stages of pre-amp limit bandwidth Optimum value of stages 2-4 NN00N2001N0NN3dB3dB0 AAA 1j / 1 / AA , 212N stages.

7 Vishal Saxena -17- Pre-amp (PA) Autozeroing AVos 1 2 2'ViVoCM1M2M3M4Vi+Vi-M5Vo+Vo- 2'M6,,OS pre ampOS inA Finite preamp gain :VV,,,22222OS preOS latchOS inprepreAA VVV For the overall Comparator : Vishal Saxena -18- Pre-amp Design : Pull-up load NMOS pull-up suffers from body effect, affecting gain accuracy PMOS pull-up is free from body effect, but subject to P/N mismatch Gain accuracy is the worst for resistive pull-up as resistors (poly, diffusion, well, etc.) don t track transistors; but it is fast! M1M2Vi+Vi-Vo+Vo-Pull-up L1mLm1 VLWLWggA:uppull diode NMOS L1pnmLm1 VLWLW ggA:uppull diode PMOS Lm1 VRgA:uppull Resistor Vishal Saxena -19- Pre-amp Design : More Gain Ip diverts current away from PMOS diodes (M3 & M4), reducing (W/L)3 Higher gain without CMFB Needs biasing for Ip M3 & M4 may cut off for large Vin, resulting in a slow recovery M1M2M3M4Vi+Vi-Vo+Vo-IpIpI 31ppnm3m1 VLWLWI2I2I ggA Vishal Saxena -20- Faster Settling Pre-amp NMOS diff-pair loaded with PMOS diodes and a PMOS cross-coupled latch High DM gain, low CM gain, good CMRR Simple, no CMFB required (W/L)34 > (W/L)56 needs to be ensured for stability Ref: K.

8 Bult and A. Buchwald, An embedded 240-mW 10-b 50-MS/s cmos ADC in 1-mm2, JSSC, vol. 32, pp. 1887-1895, issue 12, 1997. M1M2M7M3M4Vi+Vi-Vo+Vo-M5M6 Vidgm1 Vidro11gm3ro3-1gm5ro5 Vod3rg//r//r//rg1//g1g A:gain DMo1m1o5o3o1m5m3m1dmV Vishal Saxena -21- Pre-amp Example NMOS diff. pair loaded with PMOS diodes and resistors High DM gain, low CM gain, good CMRR Simple, no CMFB required Gain not well-defined Ref: Song et al., A 1 V 6 b 50 MHz current-interpolating cmos ADC, in Symp. VLSI Circuits, 1999, pp. 79-80. M1M2M5M4M3Vi+Vi-Vo+Vo-RLRLX Vishal Saxena -22- Pre-amp Example NMOS diff. pair loaded with PMOS Current mirror Simple CMFB circuit Gain is well-defined Ref: V.

9 Srinivas, S. Pavan, A. Lachhwani, and N. Sasidhar, A Distortion Compensating Flash Analog-to-Digital Conversion technique ," IEEE JSSC, vol. 41, no. 9, pp. 1959-1969, Sep. 2006. Vishal Saxena -23- Latch Design Regenerative latches for faster settling See lecture notes At least one cross-coupled regenerative core Local positive feedback Numerous methods for applying the input initial signal to regenerate upon Latches can have large static and dynamic offsets Large Regenerative gain for resolving small inputs Metastability (wrong or incomplete decisions) when latch can t make decision Pre-amp can be used for amplifying the inputs (slower tracking BW)

10 One size doesn t fit all applications Speed vs power consumption trade-off Vishal Saxena -24- Static Latch Active pull-up and pull-down full cmos logic levels Very fast! Q+ and Q- are not well defined in reset mode ( = 1) Large short-circuit current in reset mode Zero DC current after full regeneration Supply is very noisy M6M5M7Q+Q- Vi+Vi-M1M2M3M4 Vishal Saxena -25- Semi-Dynamic Latch M6M5M7 M8Vi+Vi-M1M2M3M4Q+Q- Diode divider disabled in reset mode less short-circuit current Pull-up not as fast Q+ and Q- are still not well defined in reset mode ( = 1) Zero DC current after full regeneration Supply still very noisy Vishal Saxena -26- Dynamic Latch M4M3 Vi+Vi-M7M8M5M6M1Q+Q-M2M9M10 Zero DC current in reset mode Q+ and Q- are both reset to 0 Full logic level after regeneration Slow Vishal Saxena -27- Dynamic Latch 2 Vi+Vi-M7M8M5M6M1Q+Q-M2M9M10 M4M3 Zero DC current in reset mode Q+ and Q- are both reset to 0 Full logic level after regeneration Slow Ref: T.