MSC8256 Six-Core Digital Signal Processor - Data …

FC-PBGA 78329 mm 29 mmFreescale SemiconductorData Sheet 2008 2013 Freescale Semiconductor, Inc. All rights Number: MSC8256 Rev. 6, 7/2013 Six StarCore SC3850 DSP subsystems, each with an SC3850 DSP core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, unified 512 Kbyte L2 cache configurable as M2 memory in 64 Kbyte increments, memory management unit (MMU), extended programmable interrupt controller (EPIC), two general-purpose 32-bit timers, debug and profiling support, low-power Wait, Stop, and power-down processing modes, and ECC/EDC support. Chip-level arbitration and switching system (CLASS) that provides full fabric non-blocking arbitration between the cores and other initiators and the M2 memory, shared M3 memory, DDR SRAM controllers, device configuration control and status registers, and other targets. 1056 Kbyte 128-bit wide M3 memory, 1024 Kbytes of which can be turned off to save power. 96 Kbyte boot ROM. Three input clocks (one global and two differential).

MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 6 Pin Assignment 4 Freescale Semiconductor 1 Pin Assignment This section includes diagrams of the MSC8256 package ball grid array layouts and tables showing how the pinouts are

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