MSC8256 Six-Core Digital Signal Processor - Data …

1 FC-PBGA 78329 mm 29 mmFreescale SemiconductorData Sheet 2008 2013 Freescale Semiconductor, Inc. All rights Number: MSC8256 Rev. 6, 7/2013 Six StarCore SC3850 DSP subsystems, each with an SC3850 DSP core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, unified 512 Kbyte L2 cache configurable as M2 memory in 64 Kbyte increments, memory management unit (MMU), extended programmable interrupt controller (EPIC), two general-purpose 32-bit timers, debug and profiling support, low-power Wait, Stop, and power-down processing modes, and ECC/EDC support. Chip-level arbitration and switching system (CLASS) that provides full fabric non-blocking arbitration between the cores and other initiators and the M2 memory, shared M3 memory, DDR SRAM controllers, device configuration control and status registers, and other targets. 1056 Kbyte 128-bit wide M3 memory, 1024 Kbytes of which can be turned off to save power. 96 Kbyte boot ROM. Three input clocks (one global and two differential).

2 Five PLLs (three global and two Serial RapidIO PLLs). Two DDR controllers with up to a 400 MHz clock (800 MHz data rate), 64/32 bit data bus, supporting up to a total 2 Gbyte in up to four banks (two per controller) and support for DDR2 and DDR3. DMA controller with 32 unidirectional channels supporting 16 memory-to-memory channels with up to 1024 buffer descriptors per channel, and programmable priority, buffer, and multiplexing configuration. It is optimized for DDR SDRAM. Up to four independent TDM modules with programmable word size (2, 4, 8, or 16-bit), hardware-base A-law/ -law conversion, up to Mbps data rate for each TDM link, and with glueless interface to E1 or T1 framers that can interface with H- devices, TSI, and codecs such as AC-97. High-speed serial interface that supports two Serial RapidIO interfaces, one PCI Express interface, and two SGMII interfaces (multiplexed). The Serial RapidIO interfaces support 1x/4x operation up to Gbaud with a single messaging unit and two DMA units.

3 The PCI Express controller supports 32- and 64-bit addressing, x4, x2, and x1 link. QUICC Engine technology subsystem with dual RISC processors, 48 Kbyte multi-master RAM, 48 Kbyte instruction RAM, supporting two communication controllers for two Gigabit Ethernet interfaces (RGMII or SGMII), to offload scheduling tasks from the DSP cores, and an SPI. I/O Interrupt Concentrator consolidates all chip maskable interrupt and non-maskable interrupt sources and routes then to INT_OUT, NMI_OUT, and the cores. UART that permits full-duplex operation with a bit rate of up to Mbps. Two general-purpose 32-bit timers for RTOS support per SC3850 core, four timer modules with four 16-bit fully programmable timers, and eight software watchdog timers (SWT). Eight programmable hardware semaphores. Up to 32 virtual interrupts and a virtual NMI asserted by simple write access. I2C interface. Up to 32 GPIO ports, sixteen of which can be configured as external interrupts.

4 Boot interface options include Ethernet, Serial RapidIO interface, I2C, and SPI. Supports standard JTAG interface Low power CMOS design, with low-power standby and power-down modes, and optimized power-management circuitry. 45 nm SOI CMOS Digital Signal Processor MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 6 Freescale Semiconductor2 Table of Contents1 Pin Assignment.. ball Layout Diagram .. List By ball Location..52 Electrical Characteristics .. Ratings .. Operating Conditions .. Characteristics .. Requirements .. Electrical Characteristics .. Timing Characteristics..373 Hardware Design Considerations .. Supply Ramp-Up Sequence.. Power Supply Design Considerations .. and Timing Signal Board Layout Considerations AC-Coupled Serial Link Connection Example .. Guidelines .. to Selecting Connections for Remote Power Supply Sensing ..644 Ordering Information..675 Package Information ..686 Product Documentation ..697 Revision History.

5 69 List of FiguresFigure 1. MSC8256 Block Diagram .. 3 Figure 2. StarCore SC3850 DSP Subsystem Block Diagram .. 3 Figure 3. MSC8256 FC-PBGA Package, Top View .. 4 Figure 4. Differential Voltage Definitions for Transmitter or Receiver .. 29 Figure 5. Receiver of SerDes Reference Clocks .. 30 Figure 6. SerDes Transmitter and Receiver Reference Circuits.. 31 Figure 7. Differential Reference Clock Input DC Requirements (External DC-Coupled) .. 32 Figure 8. Differential Reference Clock Input DC Requirements (External AC-Coupled) .. 32 Figure 9. Single-Ended Reference Clock Input DC Requirements 33 Figure Transmitter DC Measurement Circuit.. 35 Figure and DDR3 SDRAM Interface Input TimingDiagram .. 38 Figure to MDQS Timing .. 39 Figure SDRAM Output Timing .. 40 Figure and DDR3 Controller Bus AC Test Load.. 40 Figure and DDR3 SDRAM Differential Timing Specifications .. 40 Figure Measurement Points for Rise and Fall Time 42 Figure Measurement Points for Rise and Fall Time Matching.

6 42 Figure Frequency Sinusoidal Jitter Limits .. 46 Figure AC Test/Measurement Load .. 46 Figure Receive Signals .. 48 Figure Transmit Signals .. 49 Figure AC Test Load .. 49 Figure AC Test Load .. 50 Figure Management Interface Timing .. 51 Figure AC Timing and Multiplexing .. 52 Figure AC Test Load .. 53 Figure AC Timing in Slave Mode (External Clock) .. 53 Figure AC Timing in Master Mode (Internal Clock) .. 53 Figure Clock Input Timing .. 54 Figure Scan (JTAG) Timing .. 55 Figure Access Port Timing .. 55 Figure Timing .. 55 Figure Ramp-Up Sequence with VDD Ramping Before VDDIO and CLKIN Starting With VDDIO .. 56 Figure Ramp-Up Sequence .. 58 Figure Connection in Functional Application .. 58 Figure Connection in Debugger Application .. 58 Figure Supplies .. 59 Figure PLL Supplies .. 60 Figure AC-Coupled SGMII Serial Link Connection Example.. 60 Figure Mechanical Information, 783- ball FC-PBGA Package.

7 68 MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 6 Freescale Semiconductor3 Figure 1. MSC8256 Block DiagramFigure 2. StarCore SC3850 DSP Subsystem Block DiagramJTAGRMUNote: The arrow direction indicates master or Interface 64/32-bit4 TDMsDMAI/O-InterruptConcentratorUARTC locksTimersResetSemaphoresOther DDRCLASS High-Speed Serial InterfaceModulesQUICCE ngine Four TDMs 256-Channels each4x GbaudBoot ROMI2 CVirtualInterruptsControllerSPIDMAS erialDMAS erial4x GbaudSix DSP Cores at 1 GHz or 800 MHzSGMIITw o S G M I IRGMII RGMIIM3 Memory1056 KbytePCI-EX 1x/2x/4xSubsystemDual RISC ProcessorsEthernetEthernetSPISC3850 DSP Core512 Kbyte32 Kbyte32 KbyteL1 ICacheL1 DCacheL2 Cache / M2 MemoryRapidIORapidIODDR Interface 64/32-bitDDRC ontrollerPCIExprSerDes 1 SerDes 2x2Tw o S G M I I32 KbyteAddressTranslationTa s kProtection32 Kbyte(WTB)(WBB)EPICI nterruptsP-bus 128 bitXa-bus 64 bitXb-bus 64-bitDQBusDebug SupportOCE30512 Kbyte L2 Cache / M2 MemoryMMUT imer128 bits master IQBusDPUSC3850 CoreTWBW rite-ThroughBufferWrite-BackBufferInstru ctionCacheDataCachebus to CLASS128 bits slave bus from CLASSMSC8256 Six-Core Digital Signal Processor Data Sheet, Rev.

8 6 Pin AssignmentFreescale Semiconductor41 Pin AssignmentThis section includes diagrams of the MSC8256 package ball grid array layouts and tables showing how the pinouts are allocated for the ball Layout DiagramThe top view of the FC-PBGA package is shown in Figure 3 with the ball location index 3. MSC8256 FC-PBGA Package, Top ViewMSC8256 Top View1342567810151312119 AGAFAEADACABAAYWVUTRPNMLKJHGFEDCBA141617 1819202122232425262728 AHMSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 6 Freescale List By ball LocationTa b l e 1 presents the Signal list sorted by ball number. When designing a board, make sure that the power rail for each Signal is appropriately considered. The specified power rail must be tied to the voltage level specified in this document if any of the related Signal functions are used (active)Note:The information in Ta b l e 1 and Ta b l e 2 distinguishes among three concepts. First, the power pins are the balls of the device package used to supply specific power levels for different device subsystems (as opposed to signals).

9 Second, the power rails are the electrical lines on the board that transfer power from the voltage regulators to the device. They are indicated here as the reference power rails for Signal lines; therefore, the actual power inputs are listed as N/A with regard to the power rails. Third, symbols used in these tables are the names for the voltage levels (absolute, recommended, and so on) and not the power supplies themselves. Table 1. Signal List by ball Number ball NumberSignal Name1,2 Pin Type10 Power Rail NameA2M2 DQS3I/OGVDD2A3M2 DQS3I/OGVDD2A4M2 ECC0I/OGVDD2A5M2 DQS8I/OGVDD2A6M2 DQS8I/OGVDD2A7M2A5 OGVDD2A8M2CK1 OGVDD2A9M2CK1 OGVDD2A10M2CS0 OGVDD2A11M2BA0 OGVDD2A12M2 CASOGVDD2A13M2DQ34I/OGVDD2A14M2 DQS4I/OGVDD2A15M2 DQS4I/OGVDD2A16M2DQ50I/OGVDD2A17M2 DQS6I/OGVDD2A18M2 DQS6I/OGVDD2A19M2DQ48I/OGVDD2A20M2DQ49I/ OGVDD2A21 VSSG roundN/AA22 ReservedNC A23 SXPVDD1 PowerN/AA24 SXPVSS1 GroundN/AA25 ReservedNC A26 ReservedNC A27 SXCVDD1 PowerN/AA28 SXCVSS1 GroundN/AB1M2DQ24I/OGVDD2B2 GVDD2 PowerN/AB3M2DQ25I/OGVDD2B4 VSSG roundN/AB5 GVDD2 PowerN/AB6M2 ECC1I/OGVDD2 MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev.

10 6 Freescale Semiconductor6B7 VSSG roundN/AB8 GVDD2 PowerN/AB9M2A13 OGVDD2B10 VSSG roundN/AB11 GVDD2 PowerN/AB12M2CS1 OGVDD2B13 VSSG roundN/AB14 GVDD2 PowerN/AB15M2DQ35I/OGVDD2B16 VSSG roundN/AB17 GVDD2 PowerN/AB18M2DQ51I/OGVDD2B19 VSSG roundN/AB20 GVDD2 PowerN/AB21 ReservedNC B22 ReservedNC B23SR1_TXD0 OSXPVDD1B24SR1_TXD0 OSXPVDD1B25 SXCVDD1 PowerN/AB26 SXCVSS1 GroundN/AB27SR1_RXD0 ISXCVDD1B28SR1_RXD0 ISXCVDD1C1M2DQ28I/OGVDD2C2M2DM3 OGVDD2C3M2DQ26I/OGVDD2C4M2 ECC4I/OGVDD2C5M2DM8 OGVDD2C6M2 ECC2I/OGVDD2C7M2 CKE1 OGVDD2C8M2CK0 OGVDD2C9M2CK0 OGVDD2C10M2BA1 OGVDD2C11M2A1 OGVDD2C12M2 WEOGVDD2C13M2DQ37I/OGVDD2C14M2DM4 OGVDD2C15M2DQ36I/OGVDD2C16M2DQ32I/OGVDD2 C17M2DQ55I/OGVDD2C18M2DM6 OGVDD2C19M2DQ53I/OGVDD2C20M2DQ52I/OGVDD2 C21 ReservedNC Table 1. Signal List by ball Number (continued) ball NumberSignal Name1,2 Pin Type10 Power Rail NameMSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 6 Freescale Semiconductor7C22SR1_IMP_CAL_RXISXCVDD1C 23 SXPVSS1 GroundN/AC24 SXPVDD1 PowerN/AC25SR1_REF_CLKISXCVDD1C26SR1_REF _CLKISXCVDD1C27 ReservedNC C28 ReservedNC D1 GVDD2 PowerN/AD2 VSSG roundN/AD3M2DQ29I/OGVDD2D4 GVDD2 PowerN/AD5 VSSG roundN/AD6M2 ECC5I/OGVDD2D7 GVDD2 PowerN/AD8 VSSG roundN/AD9M2A8 OGVDD2D10 GVDD2 PowerN/AD11 VSSG roundN/AD12M2A0 OGVDD2D13 GVDD2 PowerN/AD14 VSSG roundN/AD15M2DQ39I/OGVDD2D16 GVDD2 PowerN/AD17 VSSG roundN/AD18M2DQ54I/OGVDD2D19 GVDD2 PowerN/AD20 VSSG roundN/AD21 SXPVSS1 GroundN/AD22 SXPVDD1 PowerN/AD23SR1_TXD1 OSXPVDD1D24SR1_TXD1 OSXPVDD1D25 SXCVSS1 GroundN/AD26 SXCVDD1 PowerN/AD27SR1_RXD1 ISXCVDD1D28SR1_RXD1 ISXCVDD1E1M2DQ31I/OGVDD2E2M2DQ30I/OGVDD2 E3M2DQ27I/OGVDD2E4M2 ECC7I/OGVDD2E5M2 ECC6I/OGVDD2E6M2 ECC3I/OGVDD2E7M2A9 OGVDD2E8M2A6 OGVDD2 Table 1.