Set-Reset (SR) Latch

C. E. Stroud, Dept. of ECE, Auburn of a Flip-FlopELEC 4200 Set-Reset (SR) LatchAsynchronousLevel sensitivecross-coupled Nor gatesactive high inputs (only one can be active)cross-coupled Nand gatesactive low inputs (only one can be active)SRQ+Q+Function00 QQStorage State01 0 1 Reset10 1 0 Set110-?0-?Indeterminate StateSRQ+Q+Function001-?1-?Indeterminate State01 1 0 Set10 0 1 Reset11 QQStorage StateSRQQSRQQC. E. Stroud, Dept. of ECE, Auburn of a Flip-FlopELEC 4200 Enabled Set-Reset (SR) LatchAsynchronousLevel sensitivecross-coupled Nor gatesactive high inputs (S & R cannot be active)cross-coupled Nand gatesactive low inputs (S & R cannot be active)ESRQ+Q+Function0xxQQStorage State100 QQStorage State101 0 1 Reset110 1 0 Set1110-?0-?Indeterminate StateESRQ+Q+Function0001-?1-?Indetermina te State001 1 0 Set010 0 1 Reset011 QQStorage State1xxQQStorage StateSRQQESRQQEC. E. Stroud, Dept. of ECE, Auburn of a Flip-FlopELEC 4200 Transparent D LatchAsynchronousLevel sensitivecross-coupled Nor gatesactive high enable (E)cross-coupled Nand gatesactive low enable (E)EDQ+Function0xQStorage State10 0 Transparent Mode11 1 Transparent ModeEDQ+Function1xQStorage State00 0 Transparent Mode01 1 Transparent ModeDQQEQQDEC.

Hold time (th)= minimum time input data must be held valid after active edge of clock Clock-to-output delay (tco)= maximum time before output data is valid with respect to active edge of clock Set-up or Hold Time violation => metastability (Q & Q go to intermediate voltage values which are eventually resolved to an unknown state)

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  Input, Voltage

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