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SystemVerilog Assertions (SVA) Assertion can be used to ...

SystemVerilog Assertions (SVA) Ming-Hwa Wang, COEN 207 SoC (System-on-Chip) Verification Department of Computer Engineering Santa Clara University Introduction Assertions are primarily used to validate the behavior of a design Piece of verification code that monitors a design implementation for compliance with the specifications Directive to a verification tool that the tool should attempt to prove/assume/count a given property using formal methods Capture the design intent more formally and find specification error earlier Find more bugs and source of the bugs faster Encourage measurement of

• Notice that, at clock tick 5, the simulation value transitions to high. However, the sampled value is low • Sequence layer: build on top of Boolean expression layer, and describe sequence made of series of events and other sequences • Linear sequence: absolute timing relation is known • Nonlinear sequence

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