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Asynchronous & Synchronous Reset Design Techniques - …

Asynchronous & Synchronous ResetDesign Techniques - Part DeuxClifford E. CummingsDon MillsSteve GolsonSunburst Design , EngineeringTrilobyte paper will investigate the pros and cons of Synchronous and Asynchronous resets. It willthen look at usage of each type of Reset followed by recommendations for proper usage of Boston 2003 Asynchronous & Synchronous ResetRev Techniques - Part IntroductionThe topic of Reset Design is surprisingly complex and poorly emphasized. Engineering schoolsgenerally do an inadequate job of detailing the pitfalls of improper Reset Design . Based on ourindustry and consulting experience, we have compiled our current understanding of issuesrelated to Reset - Design and for this paper have added the expertise of our colleague Steve Golson,who has done some very innovative Reset Design work. We continually solicit and welcome anyfeedback from colleagues related to this important Design presented our first paper on Reset issues and Techniques at the March 2002 SNUG conference[4] and have subsequently received numerous email responses and questions relatedto Reset Design obviously did not adequately explain all of the issues related to the Asynchronous resetsynchronizer circuit because many of the emails we have received have asked if there aremetastability problems related to the described circuit.

Each Verilog procedural block or VHDL process should model only one type of flip-flop. In other words, a designer should not mix resetable flip-flops with follower flip-flops (flops with no resets) in the same procedural block or process[14]. Follower flip-flops are flip-flops that are simple data shift registers.

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