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System on Chip Design and Modelling - University of …

System on ChipDesign and ModellingUniversity of CambridgeComputer LaboratoryLecture NotesDr. David J Greaves(C) 2011 All Rights Reserved IIComputer Science TriposEaster Term SOC Design : 2010/11: 12 LECTURES TO CST IICST-II SoC D/M Lecture Notes 2010/11 (1) Register Transfer Language (RTL) (4) Folding, Retiming & Recoding (5) Protocol and Interface (6) SystemC Components (7) Basic SoC Components (9) ESL: Electronic System Level Modelling (10) Transactional Level Modelling (TLM) (11) ABD - Assertion-Based Design (12) Network On chip and Bus Structures. (13) SoC Engineering and Associated Tools (14) Architectural Design Exploration (16) High-level Design Capture and Design : 2010/11: 12 Lectures to CST IIA current-day System on a chip (SoC) consists of several different microprocessor subsystems together withmemories and I/O interfaces.

Event-driven simulation with and without delta cycles, ba- ... Further tools used for design of FPGA and ASIC (timing and power modelling, place and route, memory generators, power gating, clock tree, self-test and scan insertion). ... Verilog and VHDL are completely equivalent as register transfer languages (RTLs). Both support simulation and ...

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