8-by-8 Bit Shift/Add Multiplier - Concordia University

8-by-8 Bit Shift/Add MultiplierGiovanni D AliesioID: 4860519 Digital Design & SynthesisCOEN 6501 Department ofElectrical & Computer EngineeringConcordia UniversityDecember 20038-by-8 Bit Shift/Add MultiplierGiovanni D Aliesio2 Table of Contents1 INTRODUCTION .. DESIGN 42 GENERAL REQUIREMENTS ..63 DESIGN SPECIFICATIONS .. CONTROLLER & MULTIPLICAND BLOCK & Multiplier /RESULT BLOCK & ADDER & Multiplier Bench .. & 164 DESIGN ENHANCEMENTS .. PLACE & DESIGN ADDER 32-BIT 215 CONCLUSION.

The associated VHDL source code is included in Appendix A: VHDL Source Code. 3.1.2 Simulation & Timing The controller is synchronous to the clock and transitions through the various states occur on the rising clock edge. As can be seen from the timing diagram in Figure 3-3, the Start signal

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  Simulation, Timing, Shifts, Multiplier, Vhdl, 8 bit shift add multiplier

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