AXI IIC Bus Interface v2 - Xilinx
The LogiCORE™ IP AXI IIC Bus Interface connects to the AMBA® AXI specification and provides a low-speed, two-wire, serial bus interface to a large number of popular devices. This product specification defines the architecture, hardware (signal) interface, software (register) interface, and parameterization options for the AXI IIC Bus
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japan.xilinx.comDevice Name AU10P AU15P AU20P AU25P System Logic Cells (K) 96 170 238 308 CLB Flip-Flops (K) 88 156 218 282 CLB LUTs (K) 44 78 109 141 Max. Dist. RAM (Mb) 1.0 2.5 3.2 4.7 Total Block RAM (Mb) 3.5 5.1 7.0 10.5 36K Block RAM Blocks 100 144 200 300 UltraRAM (Mb) – – – – Clock Management Tiles (CMTs) 3 3 3 4 DSP Slices 400 576 900 1,200
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japan.xilinx.com&PSGO % & ' XL XL ¥SSVW Meenakshi Tech Park, Survey o. 3 achibowli(V), Seri Lingampally (M), Hyderabad -500 084 Tel 1-40-6721-4747 www.xilinx.com Learn More About Xilinx Alveo U30 Accelerator Cards Learn More About Xilinx Video SDK ReSUlt:
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japan.xilinx.comUG482 (v1.8) 2016 年 6 月 21 日 japan.xilinx.com 7 シリーズ FPGA GTP トランシーバー ユーザー ガイド 改訂履歴 次の表に、この文書の改訂履歴を示します。 日付 バージョン 内容 2012 年 1 月 3 日 1.0 初版 2012 年 2 月 21 日 1.1 図2-10、式 2-1、表2-7 で、ファクターを「N」から「N1」および「N2」に変更。
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