MMPF0100, 14 Channel Configurable Power Management ...

1 NXP Semiconductors Document Number: MMPF0100. Data sheet: Technical Data Rev. 18, 7/2019. 14 Channel Configurable Power Management integrated circuit PF0100. The PF0100 SMARTMOS Power Management integrated circuit (PMIC). provides a highly programmable/ Configurable architecture, with fully integrated Power devices and minimal external components. With up to six buck Power Management . converters, six linear regulators, RTC supply, and coin-cell charger , the PF0100 can provide Power for a complete system, including applications processors, memory, and system peripherals, in a wide range of applications. With on-chip one time programmable (OTP) memory, the PF0100 is available in pre-programmed standard versions, or non-programmed to support custom programming.

2 The PF0100 is defined to Power an entire embedded MCU. platform solution such as 6 based eReader, IPTV, medical monitoring, and home/factory automation. EP SUFFIX (E-TYPE) ES SUFFIX (WF-TYPE). 98 ASA00405D 98 ASA00589D. 56 QFN 8X8 56 QFN 8X8. Features: Four to six buck converters, depending on configuration Applications: Single/Dual phase/ parallel options Tablets DDR termination tracking mode option IPTV. Boost regulator to V output eReaders Six general purpose linear regulators Set top boxes Programmable output voltage, sequence, and timing Industrial control OTP (one time programmable) memory for device configuration Medical monitoring Coin cell charger and RTC supply Home automation/ alarm/ energy Management DDR termination reference voltage Power control logic with processor interface and event detection I2C control Individually programmable ON, OFF, and standby modes PF0100 6X.

3 VREFDDR. SW4 DDR Memory DDR MEMORY. 1000 mA INTERFACE. SW3A/B. 2500 mA. SW1A/B. 2500 mA Processor Core Voltages SW1C. 2000 mA External AMP. SW2 Microphones 2000 mA SATA - FLASH Speakers SD-MMC/ SATA NAND - NOR. SWBST NAND Mem. HDD. Interfaces 600 mA Audio Codec Control Signals Parallel control/GPIOS. I2 C Communication I2C Communication Sensors VGEN1. Camera 100 mA Camera VGEN2 GPS. 250 mA WAM. MIPI. GPS uPCIe VGEN3 MIPI. 100 mA. VGEN4 HDMI. 350 mA LDVS Display VGEN5. 100 mA. USB. LICELL VGEN6 Ethernet charger 200 mA CAN. Main Supply COINCELL. V Front USB Rear Seat Rear USB. Cluster/HUD. POD Infotaiment POD.

4 Figure 1. Simplified application diagram NXP 2019. Table of Contents 1 Orderable parts .. 4. 2 Internal block diagram .. 6. 3 Pin connections .. 7. Pinout diagram .. 7. Pin definitions .. 8. 4 General product characteristics .. 10. Absolute maximum ratings .. 10. Thermal characteristics .. 11. Power dissipation .. 11. Electrical characteristics .. 12. General specifications .. 12. Current consumption .. 13. 5 General description .. 15. Features .. 15. Functional block diagram .. 16. Functional description .. 16. Power generation .. 16. Control logic .. 16. 6 Functional block requirements and behaviors.

5 18. Start-up .. 18. Device start-up configuration .. 18. One time programmability (OTP) .. 21. OTP prototyping .. 23. Reading OTP fuses .. 23. Programming OTP fuses .. 23. 16 MHz and 32 kHz clocks .. 24. Clock adjustment .. 24. Bias and references block description .. 24. Internal core voltage references .. 24. VREFDDR voltage reference .. 25. Power generation .. 28. Modes of operation .. 28. State machine flow summary .. 30. Power tree .. 32. Buck regulators .. 34. Boost regulator .. 77. LDO regulators description .. 80. VSNVS LDO/switch .. 95. Control interface I2C block description .. 100. I2C device ID.

6 100. I2C operation .. 100. Interrupt handling .. 101. Interrupt bit summary .. 101. Specific registers .. 106. Register bitmap .. 107. PF0100. 2 NXP Semiconductors 7 Typical applications .. 118. Introduction .. 118. Application diagram .. 118. Bill of materials .. 119. PF0100 layout guidelines .. 123. General board recommendations .. 123. Component placement .. 123. General routing requirements .. 123. Parallel routing requirements .. 123. Switching regulator layout recommendations .. 124. Thermal information .. 125. Rating data .. 125. Estimation of junction temperature .. 125. 8 Packaging .. 126. Packaging dimensions.

7 126. 9 Reference section .. 133. Reference documents .. 133. 10 Revision history .. 134. PF0100. NXP Semiconductors 3. ORDERABLE PARTS. 1 Orderable parts The PF0100 is available with both pre-programmed and non-programmed OTP memory configurations. The non-programmed device uses NP as the programming code. The pre-programmed devices are identified using the program codes from Table 1, which also list the associated NXP reference designs where applicable. Details of the OTP programming for each device can be found in Table 10. Table 1. Orderable Part Variations Part Number Temperature (TA) Package Programming Reference Designs Notes MMPF0100 NPAEP NP N/A.

8 MCIMX6Q-SDP (1), (2). MMPF0100F0 AEP F0 MCIMX6Q-SDB. MCIMX6DL-SDP. MMPF0100F1 AEP F1 MCIMX6 SLEVK. (1), (2), (3). -40 C to 85 C. MMPF0100F2 AEP 56 QFN 8x8 mm - mm pitch F2 N/A. (for use in consumer E-Type QFN (full lead). MMPF0100F3 AEP applications) F3 N/A. MMPF0100F4 AEP F4 N/A (1), (2). MMPF0100F6 AEP F6 MCIMX6SX-SDB. MMPF0100 FCAEP FC N/A. (1), (2). MMPF0100 FDAEP FD MCIMX6 SLLEVK. MMPF0100 NPANES NP N/A (1), (2), (4). MCIMX6Q-SDP. MMPF0100F0 ANES F0 MCIMX6Q-SDB. MCIMX6DL-SDP. MMPF0100F3 ANES F3 N/A (1), (2). MMPF0100F4 ANES -40 C to 105 C F4 N/A. 56 QFN 8x8 mm - mm pitch (for use in extended WF-Type QFN (wettable flank).)

9 MMPF0100F6 ANES industrial applications) F6 MCIMX6SX-SDB. MMPF0100F9 ANES F9 N/A. MMPF0100 FAANES FA N/A (1), (2), (4). MMPF0100 FBANES FB N/A. MMPF0100 FCANES FC N/A (1), (2). Notes 1. For tape and reel, add an R2 suffix to the part number. 2. For programming details see Table 10. The available OTP options are not restricted to the listed reference designs. They can be used in any application where the listed voltage and sequence details are acceptable. 3. For designs using the 6 SoloLite, it is recommended to use the F3 OTP option instead of the F1 OTP option and F4 OTP option instead of the F2 OTP option.

10 4. SW2 can support an output current rating of A in NP, F9, and FA Industrial versions only (ANES suffix) when SW2 ILIM=0. PF0100. 4 NXP Semiconductors ORDERABLE PARTS. PF0100 version differences PF0100A is an improved version of the PF0100 Power Management IC. Table 2 summarizes the difference between the two versions and should be referred to when migrating from the PF0100 to the PF0100A. Note that programming options are the same for both versions of the device. Table 2. Differences between PF0100 and PF0100A. Description PF0100 PF0100A. Reading SILICON REV register at address 0x03 Reading SILICON REV register at address 0x03.