Medium-density access line, ARM® -based 32-bit MCU with …

1 This is information on a product in full production. June 2015 DocID13586 Rev 171/101 STM32F101x8 STM32F101xBMedium- density access line, ARM -based 32-bit MCU with 64 or 128 KB Flash, 6 timers, ADC and 7 communication interfacesDatasheet - production dataFeatures Core: ARM 32-bit Cortex -M3 CPU 36 MHz maximum frequency, DMIPS/MHz (Dhrystone ) performance at 0 wait state memory access Single-cycle multiplication and hardware division Memories 64 to 128 Kbytes of Flash memory 10 to 16 Kbytes of SRAM Clock, reset and supply management to V application supply and I/Os POR, PDR and programmable voltage detector (PVD) 4-to-16 MHz crystal oscillator Internal 8 MHz factory-trimmed RC Internal 40 kHz RC PLL for CPU clock 32 kHz oscillator for RTC with calibration Low power Sleep, Stop and Standby modes VBAT supply for RTC and backup registers Debug mode Serial wire debug (SWD) and JTAG interfaces DMA 7-channel DMA controller Peripherals supported: timers, ADC, SPIs, I2Cs and USARTs 1 12-bit, 1 s A/D converter (up to 16 channels) Conversion range.

2 0 to V Temperature sensor Up to 80 fast I/O ports 26/37/51/80 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant Six timers Three 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter 2 watchdog timers (Independent and Window) SysTick timer: 24-bit downcounter Up to 7 communication interfaces Up to 2 x I2C interfaces (SMBus/PMBus) Up to 3 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) Up to 2 SPIs (18 Mbit/s) CRC calculation unit, 96-bit unique ID ECOPACK packages Table 1. Device summary ReferencePart numberSTM32F101x8 STM32F101C8, STM32F101R8 STM32F101V8, STM32F101T8 STM32F101xBSTM32F101RB, STM32F101VB, STM32F101CB STM32F101 TBLQFP487 x 7 mmLQFP10014 x 14 mmLQFP6410 x 10 mmVFQFPN366 6 mmUFQFPN487 7 , STM32F101xB2/101 DocID13586 Rev 17 Contents1 Introduction .. 92 Description .. overview .. compatibility throughout the family.

3 Cortex -M3 core with embedded Flash and SRAM .. Flash memory .. (cyclic redundancy check) calculation unit .. SRAM .. vectored interrupt controller (NVIC) .. interrupt/event controller (EXTI) .. and startup .. modes .. supply schemes .. supply supervisor .. regulator .. modes .. (real-time clock) and backup registers .. watchdog .. watchdog .. timer .. timers (TIMx) .. C bus .. synchronous/asynchronous receiver transmitter (USART) .. peripheral interface (SPI) .. (general-purpose inputs/outputs) .. (analog to digital converter) .. sensor .. wire JTAG debug port (SWJ-DP) .. 203 Pinouts and pin description .. 21 DocID13586 Rev 173/101 STM32F101x8, STM32F101xBContents44 Memory mapping .. 295 Electrical characteristics .. conditions .. and maximum values .. values .. curves .. capacitor .. input voltage.

4 Supply scheme .. consumption measurement .. maximum ratings .. conditions .. operating conditions .. conditions at power-up / power-down .. reset and power control block characteristics .. reference voltage .. current characteristics .. clock source characteristics .. clock source characteristics .. characteristics .. characteristics .. characteristics .. maximum ratings (electrical sensitivity) .. current injection characteristics .. port characteristics .. pin characteristics .. timer characteristics .. interfaces .. ADC characteristics .. sensor characteristics .. 726 Package characteristics .. mechanical data .. package information .. package information .. 76 ContentsSTM32F101x8, STM32F101xB4/101 DocID13586 Rev package information .. package information .. package information .. characteristics .. document.

5 The maximum junction temperature for an application .. 917 Ordering information scheme .. 928 Revision history .. 94 DocID13586 Rev 175/101 STM32F101x8, STM32F101xBList of Tables6 List of TablesTable summary .. 1 Table features and peripheral counts (STM32F101xx Medium-density access line) .. 11 Table family .. 14 Table STM32F101xx pin definitions .. 24 Table characteristics .. 32 Table characteristics .. 33 Table characteristics.. 33 Table operating conditions .. 33 Table conditions at power-up / power-down .. 34 Table reset and power control block characteristics.. 35 Table internal reference voltage .. 36 Table current consumption in Run mode, code with data processing running from Flash .. 37 Table current consumption in Run mode, code with data processing running from RAM.. 37 Table current consumption in Sleep mode, code running from Flash or RAM .. 39 Table and maximum current consumptions in Stop and Standby modes.

6 39 Table current consumption in Run mode, code with data processing running from Flash .. 42 Table current consumption in Sleep mode, code running from Flash or RAM .. 43 Table current consumption .. 44 Table external user clock characteristics.. 45 Table external user clock characteristics .. 45 Table 4-16 MHz oscillator characteristics.. 47 Table oscillator characteristics (fLSE = kHz) .. 48 Table oscillator characteristics.. 49 Table oscillator characteristics .. 50 Table mode wakeup timings .. 50 Table characteristics .. 50 Table memory characteristics .. 51 Table characteristics .. 52 Table characteristics .. 52 Table absolute maximum ratings .. 53 Table sensitivities .. 53 Table current injection susceptibility .. 54 Table static characteristics .. 55 Table voltage characteristics .. 58 Table AC characteristics .. 59 Table pin characteristics .. 60 Table characteristics.

7 62 Table characteristics.. 63 Table frequency (fPCLK1= 36 MHz, VDD_I2C = V) .. 64 Table characteristics .. 65 Table characteristics .. 68 Table max for fADC = 14 MHz .. 69 Table accuracy - limited test conditions .. 69 List of TablesSTM32F101x8, STM32F101xB6/101 DocID13586 Rev 17 Table accuracy .. 70 Table characteristics .. 72 Table - 48-lead, 7x7 mm, mm pitch, ultra thin fine pitch quad flat package mechanical data .. 74 Table - 36-pin, 6x6 mm, mm pitch very thin profile fine pitch quad flat package mechanical data .. 77 Table - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data .. 80 Table - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data .. 83 Table - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data .. 87 Table thermal characteristics .. 90 Table information scheme .. 92 Table revision history .. 94 DocID13586 Rev 177/101 STM32F101x8, STM32F101xBList of Figures8 List of FiguresFigure Medium-density access line block diagram.

8 12 Figure tree .. 13 Figure Medium-density access line LQFP100 pinout .. 21 Figure Medium-density access line LQFP64 pinout .. 22 Figure Medium-density access line LQFP48 pinout .. 22 Figure Medium-density access line UFQPFN48 pinout.. 23 Figure Medium-density access line VFQPFN36 pinout .. 23 Figure map .. 29 Figure loading conditions .. 31 Figure input voltage .. 31 Figure supply scheme.. 31 Figure consumption measurement scheme .. 32 Figure current consumption in Run mode versus frequency (at V) - code with data processing running from RAM, peripherals enabled.. 38 Figure current consumption in Run mode versus frequency (at V) - code with data processing running from RAM, peripherals disabled .. 38 Figure current consumption on VBAT with RTC on versus temperature at different VBAT values .. 40 Figure current consumption in Stop mode with regulator in Run mode versus temperature at VDD = V and V.

9 40 Figure current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = V and V .. 41 Figure current consumption in Standby mode versus temperature at VDD = V and V .. 41 Figure external clock source AC timing diagram .. 46 Figure external clock source AC timing diagram .. 46 Figure application with an 8 MHz crystal .. 47 Figure application with a kHz crystal .. 49 Figure I/O input characteristics - CMOS port .. 56 Figure I/O input characteristics - TTL port .. 56 Figure V tolerant I/O input characteristics - CMOS port .. 57 Figure V tolerant I/O input characteristics - TTL port .. 57 Figure AC characteristics definition .. 60 Figure NRST pin protection .. 61 Figure bus AC waveforms and measurement circuit(1) .. 64 Figure timing diagram - slave mode and CPHA = 0 .. 66 Figure timing diagram - slave mode and CPHA = 1(1) .. 66 Figure timing diagram - master mode(1).

10 67 Figure accuracy characteristics .. 70 Figure connection diagram using the ADC .. 71 Figure supply and reference decoupling (VREF+ not connected to VDDA).. 71 Figure supply and reference decoupling (VREF+ connected to VDDA).. 72 Figure 7 x 7 mm, mm pitch, package outline .. 73 Figure recommended footprint .. 74 Figure marking example (package top view) .. 75 Figure - 36-pin, 6x6 mm, mm pitch very thin profile fine pitch quad flat package outline.. 76 Figure - 36-pin, 6x6 mm, mm pitch very thin profile fine pitch quad flat List of FiguresSTM32F101x8, STM32F101xB8/101 DocID13586 Rev 17package recommended footprint .. 78 Figure marking example (package top view) .. 79 Figure - 100-pin, 14 x 14 mm low-profile quad flat package outline .. 80 Figure - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint .. 81 Figure marking example (package top view) .. 82 Figure - 64-pin, 10 x 10 mm low-profile quad flat package outline.