Tips on Using Test Vectors for Atmel PLDs …

1 1 Tips on Using Test Vectors for Atmel PLDsTest Vectors are a useful method for ver-ifying designs implemented inProgrammable Logic Devices (PLDs).Test Vectors allow the designer to verify,test and debug a PLD design for properfunctionality before it is used in the sys-tem. Most PLD development softwaretools and programmers offer test vectorcapabilities so that PLDs can be func-tionally simulated via software andtested during the programming application note describes the useof test Vectors in the ABEL and CUPLHDLs (Hardware Description Lan-guages)(1). In addition, some pitfalls andprecautions on the usage of test vectorswill be discussed. When simulating yourdesign Using test- Vectors in the Atmel -ABEL or Atmel -CUPL development tool,it is important to note that the test vec-tors may not simulate the actual timingrequirements of your design.

2 The ABELor CUPL test Vectors are only used tosimulate and test the logic of your :1. Atmel -ABEL or Data I/O ABEL Version or above, and Atmel -CUPL or Logical Devices CUPL Version or illustrate the usage of the test vectorsin ABEL and CUPL HDLs, the followingexamples are included in this #1: Example Using the D , U , C and K vector valuesExample #2: Testing CombinatorialFunctionsExample #3: Testing RegisteredFunctionsExample #4: Using Sets for a group ofsignals in Test-VectorsExample #5: Repeating Vectors with theABEL @REPEAT or CUPL $REPEAT syntaxExample #6: Simulating Buried NodesExample #7: Testing Bi-Directional I/OpinsIn this application note, please pay spe-cial attention to the key notes that areindicated by the in ABELABEL allows the designer to enter testvectors within the ABEL source file byusing the TEST_VECTORS provides two functional simulators,PLASIM ( ) and JEDSIM( ) to simulate a PLDdesign.

3 The PLASIM simulator, whichsimulates the ABEL logic equations, isexecuted from the Simulate Equations , Simulate Optimized or Simulate FittedDesign command in the ABEL designenvironment. The first two commandssimulate the pre-fitted (device indepen-dent) equations. If you have the AtmelPLD fitters, you can simulate fitted equa-tions with the Simulate Fitted Design command. The second simulator avail-able in the ABEL development tool is theJEDSIM. This simulator, which isexecuted via the Simulate JEDEC command in the ABEL design environ-ment, verifies your test Vectors with thelogic data extracted from the deviceJEDEC Programmable Logic DeviceApplication NoteRev. 0479C 09/99 CMOS PLD2 Simulation Trace OptionsWith the ABEL functional simulators (PLASIM and JED-SIM), you can select the following trace options forproducing simulation FormatsThe simulation output formats available in ABEL include the Pins, Waveform, Table and Macrocell for-mats.

4 Note that this display option is detailed, andshould be used in conjunction with the Signal optionto reduce the size of the output report. The defaultoption is Table format. Trace OutputsThis option selects the simulation trace level desired,such as Brief, Detailed or Clock option. The default isthe Brief option. The Detailed and Clock options areuseful for debugging complex logic circuits. Forinstance, the Clock option generates a simulationreport that shows register values when the clock is 0, 1,and 0 again for each vector . This option is useful withthe Macrocell trace format for debugging trace options available in ABEL include Trace Signal,Trace Last vector , Trace First vector , Trace Powerup,Trace X Value, Trace Z Value and Trace .tmv options. Formore information on the ABEL simulators and the traceoptions, please refer to your ABEL User In CUPLWith CUPL, a PLD design is simulated via the CSIM( ) functional simulator.

5 This simulator simulatesthe logic equations of your design before the logic ismapped into your selected target PLD. Unlike ABEL, thetest Vectors for the CUPL are not specified within thesource file. All CUPL test Vectors must be specified in a testspecification source file with file extension .SI . Forinstance, if you have a CUPL source file , then your test- vector specification file will becalled Simulation Trace OptionsLike the ABEL simulators, the CUPL simulator CSIM hasseveral simulation trace options that you can select tocontrol the simulation outputs. The CSIM trace options isset by the $TRACE directive in the .SI file, and it rangesfrom Trace Levels 0 to 4. The default option is Level 0 thatprints only the resulting simulation results. The Trace Lev-els 1 through 4 turns on the intermediate simulation resultsfor each vector .

6 These levels are specifically used fordebugging your design. For example, Trace Level 1 printsthe intermediate results for any vector that requires morethan one evaluation pass to become stable, and Level 2shows register values when the clock is 0, 1, and 0 againfor each refer to your CUPL manual for more detailed infor-mation on the CUPL CSIM simulator and its trace of Test vector SignalsIn accordance with the standards defined by the JEDECSTANDARD No. 3-C , Table 1 shows some of the mostcommonly used JEDEC test vector values when testing aPLD device. The table also shows the ABEL and CUPL testvector values that correspond to each JEDEC vector Issues on the Programming HardwareWhen entering test Vectors in your design, it is very impor-tant to use the proper vector values. If incorrect vectorvalues are used, the Vectors may fail on the PLD program-mer even though they passed the ABEL or CUPL functionalsimulation.

7 For instance, if you use 0 and 1 vector val-ues to drive the clock pin of your design, the Vectors willprobably fail on the programmer even though they passedthe ABEL or CUPL simulation (see Recommendation #1).In addition to improper test vector usage, test vector fail-ures on PLD programmers may also be a result of theprogrammer s hardware characteristics. The programminghardware dictates the sequence in which inputs in a givenvector are applied to the device. For example, the program-mer may assert 0 and 1 input Vectors in a sequentialmanner from the first pin to the last pin, or asserts the inputvectors almost simultaneously. In addition, the programmeralso sets the transition or edge rate of the input of today s PLD programmers can drive both slow andfast edge signals because they contain both normal andhigh-speed (or clock ) input drivers.

8 Figure 1 shows thetypical waveforms of the input signals applied by PLD3 Note:1. In ABEL, you can assign the test vector values to identifiers (in the ABEL DECLARATIONS section), and then use these identifiers in the TEST_VECTORS section. The following is an example of the ABEL test vector value assignments: H, L, X, Z, D, U, C, K, F = 1, 0, .X., .Z., .D., .U., .C., .K., . 1. Typical Waveforms of Input Vectors Applied by a PLD ProgrammerTable 1. ABEL and CUPL Test vector ValuesVector In JEDEC FileDescriptionABEL(1) Test vector ValueCUPL Test vector Value0 Drive Pin Low0 01 Drive Pin Low11 CDrive Pin Pin High-Low-High, Fast Pin High, Fast UsedDDrive Pin Low, Fast UsedXOutput Not Tested, Input Defined Default Input or UsedLTest Output Low0 LHTest Output High1 HZTest Input or Output for High PLD4 Recommended vector UsageThe following recommendations will ensure:1.

9 That your test Vectors simulations results from ABEL or CUPL are consistent with the verification or testing results by the programming hardware;2. That the test- Vectors applied by the programmer are not hardware dependent. Recommendation #1:Always use the D , U , C or K vector value forclock pins or clock product terms. Do not use 0 and 1 values to clock registers. See Example #1 in theAppendix registered functions, it is very important to always usethe value D , U , C , or K to clock registers. If you use 0 and 1 input Vectors to drive the clock pin of yourdesign, the Vectors may pass the ABEL or CUPL functionalsimulation but these same Vectors may fail when they areapplied on the two problems associated with Using 0 and 1 inputvalues for clocking the registers are:1. The input data to the register may not set-up prior to the clock signal.

10 With all PLD programmers, the 0 and 1 input values are applied to the device s pin before the D , U , C or K input. This implemen-tation ensures that the input data to the registers are set-up prior to the registers receiving the clock signal. If 0 and 1 input values are used for clock-ing, then the registers could get the clock signal before the input data is set-up. This would cause incorrect input signals to be set-up and clocked into the register, resulting in a test vector failure on the that you can eliminate the input data set-up prob-lem by adding a wait-state vector prior to each 0 and 1 edge transition. However, Using 0 and 1 inputvectors to drive the clock for the registers is still not rec-ommended due the possibility of the slow edge rateinput drivers being used by the The slow transitions of the clock signals that may cause the input data to the register to be double clocked.