Digital signal processing IC for speech and audio applications

1 September 2013 Rev 31/421 TDA7590 Digital signal processing IC for speech andaudio applicationsFeatures 24-bit, fixed point, 120 MIPS DSP core Large on-board memory (128KW-24 bit) Host access to internal RAM through expansion port Access to external RAM (16Mw) through expansion port Integrated stereo, 18-bit Sigma-DELTA A/D and 20-bit D/A converters Programmable CODEC sample rate up to 48 kHz On-board PLL for core clock and converters External Flash/SRAM memory bank management I2C and SCI serial interface for external control 2 enhanced synchronous serial interface (ESSI) JTAG interface Host interface 144-pin TQFP, mm pitch Automotive temperature range(from -40 C to +85 C) applications Real time Digital speech and audio processing : speech recognition speech synthesis speech compression echo canceling noise canceling MP3 decodingDescriptionThe TDA7590 is a high performances, fully programmable 24-bit, 120 MIPS.

2 Digital signal processor (DSP), designed to support several speech and audio applications , as automatic speech recognition, speech synthesis, MP3 decoding, echo and noise , the embedded CODECs bandwidth and the generic processing engine allow to proceed also full-band audio signals. The large amount of on-chip memory (128 Kwords), together with the 16 Mwords external memory addressable and the 32 general purpose I/O pins permit to build a DSP-system avoiding the usage of an additional presence of serial and parallel interfaces allows easy connection with external devices including CODECs, DSPs, microprocessors and personal particular, the debug/JTAG interface permits the on-chip emulation of the firmware developed.

3 Further, the presence of the timers and watchdog block makes TDA7590 suitable for PWM processing and allows the integration of a system watchdog. TQFP144 Table summaryOrder codePackagePackingE-TDA7590 TQFP144 ( exposed pad down)(1)1. In ECOPACK package (see Section 8: Package information on page 22).TrayE-TDA7590 TRTape and Contents1 Block diagram .. 62 Pin description .. connection .. function .. data .. 133 Key parameters .. consumption .. (ADC/DAC) test description .. 154 Electrical specification .. maximum ratings .. characteristics for I/O pins .. 16524 bit DSP core .. 176 Memories .. 187 DSP peripherals .. audio interface (SAI) .. communication interface (SCI).

4 Interface .. interface (HI) .. and watchdog block .. cell .. 218 Package information .. 229 Appendix 1 .. 23 TDA7590 Contents 3 program .. 23 Revision history .. 41 List of tablesTDA75904/42 List of tablesTable summary .. 1 Table function .. 8 Table data.. 13 Table parameters .. 14 Table maximum ratings .. 16 Table DC operating conditions .. 16 Table interface electrical characteristics .. 16 Table revision history .. 41 TDA7590 List of figures 5/42 List of figuresFigure diagram .. 6 Figure connection (top view).

5 7 Figure mechanical data and package dimensions .. 22 Block diagramTDA75906/42 1 Block diagramFigure diagram MOZART core 120 MIPs, 32 GPIOsEBUGI nterfacePROM PRAM 16K x 24 XRAM4/8/16/14K x 24 YRAM 68/64/56/48K x 24 FLEX RAM 40K x 24 Expansion PortPLL ClockOscillator2 Channel Codec ESSIESSI/12C SCI HOST i/fTripleTimerDDBYDBDABYA BXDBXABPA BEDBEAB SAI/CCTrclksclkTDA7590 Pin description 7/422 Pin Pin connectionFigure connection (top view)144142 140 138SC11136 134 132 130 128 126 124 122 120 118 116 114 112 110143141139137SC12125121117115109135133 13112912712311911311145464749 HREQ51 IOVSS53 HAS55HA857 HAD659 HAD461 COREVSS63 HAD26567AA369 XTI71 PLL_VDDHDSWENAA1BG48 HACK50 IOVDD52 HCS54 HAD756HA968AA272 PLL_VSSIOVSS58 HAD560 COREVDD62 HAD364 HAD16670 HRWOENAA0 SRD1 STD1 SRD0DB6DB5DB4DB3 COREVSS102 COREVSS101 COREVDD100999897AB596AB195AB394AB293 IOVSSCOREVDDDB1DB2AB19AB18AB17AB16 RXDTXD108AB13107AB12106 IOVSS105 IOVDD104AB11103AB1092 IOVDD91 IOVSS90 IOVDD89 NMI2SC023SC0145 IOVDD6 IOVSS7 STD08SC109SC0010 SCLK36DE_NTESTEN313233343511 SCK112 SCK013 RESET14 SCANEN15 COREVDD16 COREVSS17 TIO018 VSSSUB19 DACOP20 REF021

6 CODEC_VDD22232425 DAC126 CODEC_VSS27 DACOM2829301AB15373839414340424482818079 787776757473888786858483AB14 XTOHAD0 ADC1 ADCOMADCOPIOVDDIOVSSTDOTMSTCKTRSTNIRQDIR QCIRQBIRQADB23DB22DB21DB15 IOVSSIOVSSCOREVSSCOREVDDDB19DB18DB17DB16 IOVDDDB20DB14DB13DB12DB11DB10DB9 IOVSSIOVDDDB8DB7 TDIEXTDACLKBRBBIOVDDAB4AB6AB7DB0AB0 IOVDDAB9AB8 Pin descriptionTDA75908/42 Pin function Table function N NameTypeDescription1 SRD1/TI02I/OSerial receive data. Serial input data for receiver. Timer 2 transmit data. Serial output data from control frame sync only in asynchronous mode, transmitter and receiver frame sync in synchronous control 1. Receive frame sync in asynchronous mode, outputfrom transmitter 2 or serial flag 1 in synchronous data output (input/output).

7 Debug request input and acknowledge interrupt/ PINIT. Used to enable the PLL during RESET and as a non-maskable interrupt at all other receive data. Serial input data for power Transmit Data. Serial output data from serial control 0. Receive clock in asynchronous mode, output from transmitter or serial flag in synchronous SCL serial clock control 0. Receive clock in asynchronous mode, output from transmitter 1 or serial flag 0 in synchronous receive data. Receives byte-oriented serial read enable. Transmits serial data from SCI transmit shift serial clock. Input or output clock from which data is transferred in synchronous mode and from which the transmit and/or receive baud rate is derived in asynchronous clock.

8 Serial bit clock for transmitter only in asynchronous mode, serial bit clock for both receiver and transmitter in synchronous 1 clock. Serial bit clock for transmitter only in asynchronous mode, serial bit clock for both receiver and transmitter in synchronous reset. A low level applied to RESET_N input initializes the enable. When active with TESTEN also active, controls the shifting of the internal scan enable. When active, puts the chip into test mode and muxes the XTI clock to all flip-flops. When SCANEN is also active, the scan chain shifting is power 0 substrate description 9/4225 DAC1 ODAC1 left single analog negative right differential analog positive right differential analog power left single analog negative right differential analog positive right differential analog DAC clock.

9 Optional external clock source from which LRCLK and SCLK can be oscillator input. External clock input or crystal oscillator output. Crystal oscillator output power ground data strobe. Polarity programmable Host data strobe input for single strobe mode. Polarity programmable Host write strobe input for double strobe read/write. Host read/write for single strobe bus mode. Polarity programmable Host read data strobe for double strobe acknowledge. Polarity programmable host interrupt acknowledge for single host request mode. Polarity programmable host receive request interrupt for double host request request. Polarity programmable host request interrupt for single host request mode. Polarity programmable host transfer request interrupt for double host request power chip select.

10 Polarity programmable host chip select for non-multiplexed mode. Host address Line 10 for multiplexed address 9. Address line 9 in multiplexed mode otherwise address line 2 in non-multiplexed address 8. Address line 8 in multiplexed mode otherwise address line 1 in non-multiplexed address strobe. Address strobe for multiplexed bus or Address 0 for non [7]I/OHost 8-bit data line 7. Host data bus and/or address lines when in multiplexed function (continued)N NameTypeDescriptionPin descriptionTDA759010/42 52 HAD[6]I/OHost 8-bit data line 6. Host data bus and/or address lines when in multiplexed [5]I/OHost 8-bit data line 5. Host data bus and/or address lines when in multiplexed [4]I/OHost 8-bit data line 4.