Calibrationand Dynamic Matching in Data Converters

1 Calibration and Dynamic Matching in data ConvertersKenneth C. Dyer, John P. Keane1, and Stephen H. Lewis21 Keysight Technologies Inc., Santa Clara, CA USA2 University of California, Davis, CA USA1 Outline Calibration of DAC Mismatch Dynamic Element Matching Calibration of Pipelined ADCs Calibration of Time-Interleaved ADCs2 ADCs use DACsVin+ComparatorLogicOutDAC SAR ADCVin+ Integrator + ADC DACs can limit ADC performance DAC calibration improves ADCs3 Laser Trimming an R-2R Ladder DACIout2RN 2RN 1 RRN RIN 2BN 22RN 1IN 1BN 12 RNINBNIT2 RCal Holloway and Norton, ISSCC76 [1] IfIN 1<IN+IT, trimRN IfIN 1>IN+IT, trim2RN 1 Single-pass trim (start on right and move to left) improves linearity4 Fuse Trimming Early ref.

2 McGlinchey, ISSCC82 [2] (Trims at wafer sort)R0 VBIAS1 VBIAS3SR bitEnableF0 VDD=5VR1 PolyOutputSR bitEnableF1 de Wit et al., JSSC 4/93 [3] (Uses low volt pulses after packaging) Fuses may not open completely and may heal Blow eitherR0orR1and compare to each other Customers like trimming5 Analog Foreground Cal. of Capacitor MismatchC1 VFSVtop=0C2t<0C1 VtopC2 VFSt>0tVtopC2>C1C1> Lee et al., JSSC 12/84 [4] Used to improve linearity in a charge-redistribution SAR ADC Vtopdriven back to zero by R-string DAC (low DNL) Errors measured at powerup and can be remeasured any time Does not require lasers or non-volatile memory Does not require special fab or test equipment6 Analog Background Cal.

3 Of Current Mismatch+Vgs1 I1+Vgsi Ii+Vgsn InSwitch arrayIoutTo calibrateIiIi=IrefIref+Vgsi Groeneveld et al., JSSC 12/89 [5] Adjusts eachVgsto setI1=..=Ii=..=In=Iref Uses an extra current source Early example of background calibration7 Quadratic Voltage CoefficientAnalogInputDigital OutputIdealWith QVCV1Dv1V2Dv2 VrDvrVrhR1R2 Vrl+V1 +V2 Vr+ To top plate of main arrayCgVoNonlin Function GenVo=k(V2r V2in)VinVrVnVp Tan et al., JSSC 12/90 [6] C C0(1+ 1V+ 2V2) Quadratic VC causes 3rd order error (Q= C dV) Cancel error with equal and opposite correction voltage Cal on chip withV1 V2 Vr/2andV1+V2=Vr Use error=Dv1+Dv2 Dvrto setCgto cal gain8 Digital Foreground Calibration of DAC MismatchVin H1(z)4-bitADSC24 16-bitEPROMOut4-bitDAC 4164 Cataltepe et al.

4 , ISCAS 1989 [7] If loop gain , DAC output=Vinon average If DAC is nonlinear, ADSC output has inverse nonlinearity Program EPROM with same nonlinearity to linearize the modulator Reconfigure as a single-bit to measure DAC in foreground In converter , downsample after EPROM Early example of on-chip digital foreground calibration9 Dynamic Element MatchingIMirrorI1 I/2I2 I/2 SwitchesI3I4 Clk van de Plassche, JSSC 12/76 [8] Use matched elements with time-division multiplexing I3=I4on average even ifI16=I210 Dynamic Matching in a Delta-Sigma Element1 Unit Element88 AnalogOut1 RNG12 Carley and Kenney, CICC 1988 [9] Randomize DAC elements Decorrelate DAC elements usage from input Nonlinearity improveson average Nonlinearity white noise ILA (Leung and Sutarja, TCASII 1/92 [10]) gives shaped noise11 data -Weighted AveragingVDD+VO Code = 110 VDD+VO Code = 160 140 120 100 80 60 40 200fin/fsdB FixedRandomDWA Baird and Fiez, JSSC 12/95 [11] Only care about low-freq.

5 Noise shape error to high freq. Use DAC elements in sequence Higher-order shaping is possible12 Pipelined ADCVinSHAS tage1 GSHAVo1 Vin1 ADSCDACd1 VDAC1 StageN+ Insensitive to offset errors with redundancy Main Performance limitations:Interstage gain errorsDAC nonlinearity13 Ratio-Independent GainVi 1C2 + C1C2 + 2 C1Vo=C2C1 ViVi 3C2 + C1C2 + 4 C1Vo=2Vi Li et al., JSSC 12/84 [12] Requires high open-loop gain and 4 clock phases Reference Refreshing, Shih et al., JSSC 8/86 [13] Correlated Double Sampling, Nagaraj et al., TCAS 5/87 [14] Error Averaging, Song et al., JSSC 12/88 [15] Customers like these techniques, which improve linearity14 Analog Calibration of a Pipelined ADC 1C1C2C3C4VR +CF 2C1C2C3C4 +LogicCFVR Lin et al.

6 , JSSC 4/91 [16] Op amp is offset canceled with aux. input Compare each samp. cap toCFand adjust to match Use opamp as comparator preamp (Threshold=VR)15 Digital Calibration of a Pipelined ADCViSHA11-bADSC01-bDAC+VR/2 VR/2 +Vi VR/2 SHA<2 ViIdealCodeViMissing CodesCodeViMissing Dec LevCode Karanicolas et al., JSSC 12/93 [17] Digital cal. does not create or move decision levels Set interstage gain < 2 to avoid missing decision levels Add extra stages to introduce redundancy Then calibration can be done digitally16 Add Dither to ADC InputVin1 SHA+ + GADSC2 ADSC1 DAC1 + +Dout AccumDACGainRNGDACD ither+ Jewett et al., ISSCC97 [18] Subtractive dither improves DNL and SFDR Accumulator adjusts gain of dither DAC to remove dither17 Add Dither to ADSC Output1 SHA+ G1 ADC2 VinADSC1+ DAC1 + DoutRNG++ + + Accum1/ G1 Hilton, HP Journal 10/93 [19] Siragusa et al.

7 , Elect. Let. 3/00 [20] Accum adjusts1/ G1until G1 G1 Increases required DAC resolution18 Add Dither to ADSC Input1 SHA+ G1 ADC2 Vin+ ADSC1 DAC1 + Dout Accum1/ G1 RNG + Li and Moon, TCASII 9/03 [21] Accum adjusts1/ G1until G1 G1 Low complexity but only calibrates forVinnear ADSC1thresholds Fetterman et al., CICC 5/99 [22] (dither without calibration)19 Redundant Residue ModeVoi VRVini VRMode=1 Murmann and Boser, JSSC 12/03 [23] Requires about 1 extra bit of resolution Equivalent to adding dither to ADSC and DAC inputs Ideally both modes give identical results Background calibrates for gain errors and variation Shows that calibration can reduce power dissipation20 Tracking BandwidthVinN-bitADCDout(Vin+ Dither) AccumDitherDitherWeightnEnlargeTconverge Weight[n+1] =Weight[n] + (Vin+ Dither) Dither Steady stateSNR 1/ : Need small 1/22N Tracking Bandwidth.

8 Need large 1/Tconverge Can improve by removingVinbefore correlation21 Two-Channel or Split ADC ArchitectureVinADC1 Dither1+ + Ddither + Li and Moon, TCASII 9/03 [21] and McNeill et al., JSSC 12/05 [24] ReducesVininDdither Increases tracking bandwidth dramatically Requires little extra power dissipation if noise limited22 Calibrating with a Parallel ADCSHAFastInaccurateADCfsDSP M e+ SlowCalibratedADCfs/MDoutVinfs Wang et al. CICC 9/03 [25] and Chiu et al. TCASI 1/04 [26] UsesVinto calibrate Input SHA is not required (Wang et al., JSSC 10/09 [27]) Slow ADC: Needs high linearity (achieved through calibration) Can have high noise & low power dissipation Can have low resolution with enough dither23 DEM and ADC CalibrationSHA+ + + G1 ADC2+VinADSC1 DAC1 DAC2 DAC3 + RNG1+ RNG2 B + ErrorTable + Dout H++ Use DEM for DAC inside ADC.

9 Hilton, HPJ 10/93 [19] Galton, TCASI 3/00 [28] DAC element control bitsBare uncorrelated with ADC input, so canmeasure DAC mismatch in background by correlating with ADC output Can then correct digitally and remove with lookup table Residual DAC nonlinearity appears as noise24 Time-Interleaved ADCsVin(t)AnalogDemuxfsADC1 ADC2 ADCMD igitalMuxfs/Mfs=1/TDout(nT) Black and Hodges, JSSC 12/80 [29] Increases throughput byM Channel offset mismatches Periodic additive pattern Channel gain mismatches Amplitude modulation Channel sample-time errors Phase modulation25 Chopper-Based Offset Calibration C[m]SHA1 ADC1 AnalogInputChopping SHAS1+ Y1 C[m]a1 Notch Filter Accum V1 van der Ploeg et al.

10 , JSSC 12/01 [30] and Jamal et al., JSSC 12/02 [31] C[m]= 1 (Random, Zero Mean) Cancels SHA & ADC Offsets w/o Spectral Nulls Apply separately to each channel Used by Janssen et al. [32] and Setterberg et al., ISSCC13 [33]26 Input Dither to Measure Channel GainVin+ ADC + DoutGARNG 1-b DAC+GD AccumG Fu et al., JSSC 12/98 [34] GA G=1/GD Calibrates gain mismatch with interleaved channels Used by Setterberg et al., ISSCC13 [33]27 Extra Parallel Channel for Timing CalibrationVin(t) 1 ADC1 MADCMMuxDout(nT)Timing CalPhase 1 MClkIfs1-bitFlash ADC El-Chammas and Murmann, JSSC 4/11 [35] Uses parallel flash channel to calibrate timing errors bymaximizing correlation between flash ADC and interleaved channels28 Find Derivative (D) for Timing CalibrationVin(t) R 0 CADCt 0 CADC0 CADCi D Accum tiDelay i++ e Stepanovi c and Nikoli c, JSSC 4/13 [36] ADCtand ADC0are ref ADCs that can sample at same time as any ADCi e= D t t[new]= t[previous] (de2/d t) t[new]= t[previous]+ 2 e D D(s) =sC R/((1+sCR)(1+sC(R+ R)))