10 MH TO Z I2C PROGRAMMABLE XO/VCXO - Silicon Labs

1 Rev. 6/18 Copyright 2018 by Silicon LaboratoriesSi570/Si571Si570/Si57110 MHZ TO GHZ I2C PROGRAMMABLE XO/VCXOF eaturesApplicationsDescriptionThe si570 XO/Si571 VCXO utilizes Silicon Laboratories advanced DSPLL circuitry to provide a low-jitter clock at any frequency. The si570 /Si571 are user- PROGRAMMABLE to any output frequency from 10 to 945 MHz and select frequenciesto 1400 MHz with <1 ppb resolution. The device is programmed via an I2C serialinterface. Unlike traditional XO/VCXOs where a different crystal is required foreach output frequency, the Si57x uses one fixed-frequency crystal and a DSPLL clock synthesis IC to provide any-frequency operation.

2 This IC-based approachallows the crystal resonator to provide exceptional frequency stability andreliability. In addition, DSPLL clock synthesis provides superior supply noiserejection, simplifying the task of generating low-jitter clocks in noisy environmentstypically found in communication Block Diagram Any PROGRAMMABLE output frequencies from 10 to 945 MHz and select frequencies to GHz I2C serial interface 3rd generation DSPLL with superior jitter performance 3x better frequency stability than SAW-based oscillators Internal fixed crystal frequency ensures high reliability and low aging Available LVPECL, CMOS, LVDS.

3 And CML outputs Industry-standard 5x7 mm package Pb-free/RoHS-compliant , , or V supply SONET/SDH xDSL 10 GbE LAN/WAN ATE High performance instrumentation Low-jitter clock generation Optical modules Clock and data recoveryFixedFrequencyXO10-1400 MHzDSPLL ClockSynthesisCLK-CLK+SCLGNDOEVDDSDAVCAD CSi571 onlyOrdering Information:See page Assignments:See page 30.(Top View)Si5602Si570Si571123654 NCGNDOEVDDCLK+CLK SDASCL87123654 VCGNDOEVDDCLK+CLK SDASCL87Si570/Si5712 Rev. OF CONTENTSS ectionPage1. Detailed Block Diagrams ..32. Electrical Specifications .. 43. Functional Description.

4 Programming a New Output Frequency .. si570 Programming Procedure .. si570 Troubleshooting FAQ .. I2C Interface .. 214. Serial Port Registers .. 225. si570 (XO) Pin Descriptions .. 296. Si571 (VCXO) Pin Descriptions .. 307. Ordering Information ..318. Si57x Mark Specification ..329. Outline Diagram and Suggested Pad Layout .. 3310. 8-Pin PCB Land Pattern .. 34 Revision History .. 35Si570/Si571 Rev. Detailed Block DiagramsFigure 1. si570 Detailed Block DiagramFigure 2. Si571 Detailed Block DiagramFrequency ControlControl InterfaceNVM HS_DIV N1+DCORFREQCLKOUT+CLKOUT VDDGNDfXTAL foscMSDAOESCLRAMF requency ControlControl InterfaceNVM HS_DIV N1+DCOADCRFREQVCADCVCCLKOUT+CLKOUT VDDGNDfXTAL foscMSDAOESCLRAMSi570/Si5714 Rev.

5 Electrical SpecificationsTable 1. Recommended Operating ConditionsParameterSymbolTest ConditionMinTypMaxUnitSupply V V V CurrentIDDO utput enabledLVPECLCMLLVDSCMOS 120108999013011710898mATriState mode 6075 Output Enable (OE)2,Serial Data (SDA),Serial Clock (SCL) x VDD VVIL Temperature RangeTA 40 85 parameter specified by part number. See Section "7. Ordering Information" on page 31 for further OE pin includes a 17 k pullup resistor to VDD. See Information .Table 2. VC Control Voltage Input (Si571)ParameterSymbolTest ConditionMinTypMaxUnitControl Voltage Tuning Slope1,2,3 KVVC 10 to 90% of VDD 334590135180356 ppm/VControl Voltage Linearity4 LVCBSL 5 1+5%Incremental 10 5+10 Modulation Input ImpedanceZVC500 k Nominal Control Voltage5 VCNOM@ fO VDD/2 VControl Voltage Tuning RangeVC0 slope; selectable option by part number.

6 See "7. Ordering Information" on page For best jitter and phase noise performance, always choose the smallest KV that meets the application s minimum APR requirements. See AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR) for more KV variation is 10% of typical BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope is determined with VC ranging from 10 to 90% of Nominal output frequency set by VCNOM= 1/2 x 3. CLK Output Frequency CharacteristicsParameterSymbolTest ConditionMinTypMaxUnitProgrammable Frequency Range1,2fOLVPECL/LVDS/CML10 160 Temperature Stability1,3TA= 40 to +85 C 7 20 50 100 7+20+50+100ppmInitial Accuracy ppmAging faFrequency drift over first year 3ppmFrequency drift over 20-year life 10ppmTotal StabilityTemp stability = 7 ppm 20ppmTemp stability = 20 ppm stability = 50 ppm Pull Range1,3 APR 12 375ppmPower up Time4tOSC 10 Section "7.

7 Ordering Information" on page 31 for further Specified at time of order by part number. Three speed grades available:Grade A covers 10 to 945 MHz, 970 to 1134 MHz, and 1213 to B covers 10 to 810 C covers 10 to 280 Selectable parameter specified by part Time from power up or tristate mode to 4. CLK Output Levels and SymmetryParameterSymbolTest ConditionMinTypMaxUnitLVPECL Output Option1 VOmid-levelVDD VDD (diff) (single-ended) Output (diff) Output V option mid-level VDD V option mid-level VDD V option swing (diff) V option swing (diff) Output Option3 VOHIOH= x VDD VDDVVOLIOL=32mA time (20/80%)tR, tFLVPECL/LVDS/CML 350psCMOS with CL=15pF 1 nsSymmetry (duty cycle)SYMLVPECL:VDD V (diff) V (diff)CMOS:VDD/245 55% =50 to VDD Rterm=100 (differential).

8 3. CL=15pFSi570/Si571 Rev. 5. CLK Output Phase Jitter ( si570 )ParameterSymbolTest ConditionMinTypMaxUnitPhase Jitter (RMS)1for FOUT > 500 MHz J12 kHz to 20 MHz (OC-48) kHz to 80 MHz (OC-192) Jitter (RMS)1 for FOUT of 125 to 500 MHz J12 kHz to 20 MHz (OC-48) kHz to 80 MHz (OC-192)2 Jitter (RMS) for FOUT of 10 to 160 MHzCMOS Output Only J12 kHz to 20 MHz (OC-48)2 ps50 kHz to 20 MHz2 to AN256 for further Max offset frequencies: 80 MHz for FOUT > 250 MHz20 MHz for 50 MHz < FOUT <250 MHz2 MHz for 10 MHz < FOUT <50 6. CLK Output Phase Jitter (Si571)ParameterSymbolTest ConditionMinTypMaxUnitPhase Jitter (RMS)1,2,3 for FOUT > 500 MHz JKv = 33 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) psKv = 45 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Kv = 90 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Kv = 135 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Kv = 180 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Kv = 356 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Modes.

9 LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further For best jitter and phase noise performance, always choose the smallest KV that meets the application s minimum APR requirements. See AN266: VCXO Tuning Slope (kV), Stability, and Absolute Pull Range (APR) for more See AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO for comparison highlighting power supply rejection (PSR) advantage of Si55x versus SAW-based Single ended mode: CMOS. Refer to the following application notes for further information: AN255: Replacing 622 MHz VCSO Devices with the Si55x VCXO AN256: Integrated Phase Noise AN266: VCXO Tuning Slope (kV), Stability, and Absolute Pull Range (APR) 5.

10 Max offset frequencies: 80 MHz for FOUT > 250 MHz20 MHz for 50 MHz < FOUT <250 MHz 2 MHz for 10 MHz < FOUT <50 Jitter (RMS)2,4,5for FOUT 10 to 160 MHzCMOS Output Only JKv = 33 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 20 MHz psKv = 45 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 20 MHz Kv = 90 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 20 MHz Kv = 135 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 20 MHz Kv = 180 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 20 MHz Kv = 356 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 20 MHz Table 6.