Application Note MOS- - Alpha & Omega Semiconductor

1 Rev. Parallel Abstract: Thiapplications. examination 1. IntroduMOSFETs wsupplies and power applicimprove efficMultiple factoparameters, unbalanced cMOSFETs. reaching damgate of eachMOSFETs bythese issues 2. UnbalaUnder steadyacross (on) increabalance the current increRDS(on). At thcurrent sharinUnder switchcontrolled swimbalances, voltage, its finductances the time of dematched paragate driver dproperly bala ing Pows paper discu It investigatof PCB layouuction with low on-re motor drivercations, multipiency. ors influence asymmetric current flow iSecond, the maging levelsh MOSFET, cy exceeding and providesanced Curry-state condit. The on-resases with temcurrent amoeases in one at point, curreng amongst thing conditionwitch. Duringespecially at forward transin the PCB aevice productameters can design technianced. wer MOSusses issues tes root causuts and importesistance andrs in e-bikes, ple MOSFET ssuccessful pagate drivers, in parallel MOdrain-to-sourcs on the draincausing exceits maximums recommendrent and Votions, parallelsistance (RDSmperature.)

2 Ng multiple MMOSFET, pent will flow tohe MOSFETsns, the story isg the dynamhigher frequesconductanceall factor in totion and cannbe economicaques that enwww SFETs ininvolved in pase problems stant circuit ded fast switchelectric-motos used in pararalleling of hand poor laOSFETs can ce voltage apn of one of thessive gate-tom rated VGS. ed in Ped MOSFETsS(on)) of a MOThis known MOSFETs. ower dissipao one of the os. s very differemic process oencies. The e, total gate current and not be changeally challenginnsure that Switcharalleling MOsuch as unbaesign paramething characteor cars, powerrallel are oftehigh-speed poyout of the Pprovoke ovepplied to eachhe devices. o-source voltThis applicaParallel MOs work well, sOSFET has a phenomenonCurrent flowstion also incother MOSFEent. Generallyof switching, characteristiccharge (Qg), voltage imbaed in the applng. The beste current andplicatiohing AppOSFETs in higalanced voltaters for drivineristics are wr tools and elen necessary ower MOSFEPCB can cauer-current conh MOSFET cFinally, parasage, potentiation note conOSFET Appsharing currenpositive temn assists in s through thereases, heatiTs with a lowy speaking, amany factorcs of the MOSRDS(on), the alances.

3 Thelication, and st way to preved voltage acrn NoteDplicationgh- power , higage and curreg paralleled Mwidely used inectric lawn mto increase ETs. Variancuse a numbenditions and can actually bsitic oscillatioally damagingnducts a detaplications nt with an eqmperature coeparalleling Me path of leaing the devicwer resistancea MOSFET bers can causeSFET, includiactual drivere MOSFET pascreening MOent these probross the paraPe MOS-Decemberns h-frequency sent by taking MOSFETs. n switch-modmowers. In thcurrent capabce in the actuer of problemdamage one be different, pons can appeg one or morailed study ofual amount oefficient, meaMOSFETs asast resistancece and increae, causing theehaves like ae current anding the gate tr circuit and arameters areOSFETs to geblems is to usalleled MOSF age 1 of 8 -010r2013switching a closer de power hese high bility and al device ms. First, or more otentially ear at the re of the f each of of voltage ning that it helps e and as asing the e inherent a voltage-d voltage threshold parasitic e fixed at et exactly se proper FETs are Rev.

4 Current Understandinapplications iThreshold Voor gate driversecond MOSthe lower VGSF orward Tranoff and the Ovoltage, VGSD ifferent gateversa. Gate Chargecurrent flow MOSFETs arMOSFETs. Tcausing anot The EffeIn the gate dimpact of mrecommendethese gate reare paralleledgate of Q2. T on Note MUnbalance Rng MOSFET is an importanoltage, Gate-tr signal. A MSFET with a sS(TH) and an unsconductancOhmic region. This regioe-to-source ve (Qg): Total from drain-tore paralleled, This faster tuther unbalancect of the Gadriver circuit smismatched ged in high-freqesistors are md. R1 is the dThis creates tFMOS-010 Resulting Froparameters ant first step toto-Sourec (VGOSFET with aslightly highernbalanced cuce (gFS): In th where the Mn is governevoltages will cgate charge, o-source, will if one of the urn on causesced current cote Driver Resshown in figugate resistanquency applimatched as cldriving resistothe gate driveFigure 1.)

5 Driwwwom MOSFETand how theyo determining GS(TH)): Paralla lower gate-r VGS(TH). Thisurrent situatiohe saturation MOSFET is fued by the forcause currenthe total chasignificantly aMOSFETs hs that MOSFE ondition. sistance on ure 1, an intences. As wcations to avosely as possor connected er mismatch. ving Circuit Parametersy affect currenthe right soluleled MOSFEto-source thres results in hn. region betweully on, the drward transcont imbalancesarge requiredaffect the swhas a lower QET to handle Current Imbantional mismwill be shownvoid additionasible. In the gin series with with the Gats nt and voltageution to the prETs are normaeshold voltagigher current een the cut-ofdrain current ionductance (s during the tat the gate towitching speedQg value, it wilthe majority oalance atch has been in section al complicatiogate driver cih the gate of Qte Resistor Me balancing inroblems that mally driven byge (VGS(TH)) wiflowing throuff region wheis controlled gFS) charactetransition fromo turn-on the d of the MOSl turn on fastof the currenten created an3, the use ons, and it is rcuit shown inQ1.

6 R3 is conMismatch Pn paralleled Mmay arise. y the same gall turn on fastugh the MOSere the MOSFby the gate-teristics of them on to off aMOSFET anSFET. Whener than the ret during the trnd tested to sof gate rescritical to enn figure 1, Q1nnected to R1 age 2 of 8 MOSFET ate driver ter than a FET with FET turns to-source e device. and vice-nd enable n multiple est of the ransition, show the sistors is sure that 1 and Q2 1 and the Rev. Applicatio Figures 2a aresistor mismgate resistanflow through larger voltagehandling largto balance cuin a parallele The EffeIn high-poweoverall systecontrolled. Figure 3 showIn this circuitMOSFET tha on Note MFigure nd 2b show tmatch. Channnce. These faQ2. The hige peaks and ger peak curreurrent throughd Application ,ect of the Gaer, high-frequem. Excessivws parasitic i, the drain indat was chosenFigMOS-010 2a. Turn-On the gate-to-sonel 1 shows taster switchinher current floringing.

7 Theents during thh each MOSF, and using mte Driver Ciruency applicave stray indunductance in ductance of Qn for this simugure 3. A SimwwwWaveformsource voltagethe faster turnng times provoow through the difference bhe transitions FET during trmatching gate rcuit Layout oations, the pactance in thetwo paralleleQ1 is 40nH (Lulation. mulating Figus during turn-n-on and turnoke higher cuhe parasitic inbetween Q1 adue to the mransitions to aresistance ison Voltage Uarasitic induce drain may ced MOSFETsL1) and the incuit with Diffure 2b. Turn--on and turn-n-off times of urrent flow thrnductance in tand Q2 in figmismatched gavoid excessi the key to acUnbalance ctance of thecause the M, intentionallyductance of Qferent Drain I-Off Waveforoff that resultQ1, the resurough Q1, cothe drain andgures 2a andate driver resive stress on chieving the de PCB can nOSFET to fay skewed to sQ2 is 20nH (LInductance Prms t from the gatult of the slighmpared to thd source of Q 2b shows thsistors.)

8 It is ione of the Mdesired perfornegatively imail if they aresimulate a pooL2). AOT470 age 3 of 8 te driving htly lower e current 1 causes hat Q1 is mportant MOSFETs rmance. mpact the not well or layout. is a 75V Rev. Applicatio During turn-oand the chanparasitic indapproximatelWhen the paterm will be uhigher drain shown in figucircuit. ThisMOSFET excdriver circuit designer can 3. ManagMany designHowever, thiseven surpass on Note MFiguoff a voltage wnging current uctance is oy the same. rasitic inductaunequal. Thisvoltage on Qure 4) is also combinationceed its maxias shown in avoid these ing Potentners tend to ds approach cs the maximuInducindudi/dtMOS-010 ure 4. Simulawill be added (V = L* di/dt)optimized for ances in the ds difference, iQ1. Additionalarger when n of ringing aimum rated dsection , mismatches. tial Oscillatdirectly connecan easily caum rated gate ced by drain ctance and Q2 wwwtion Wavefoto the maxim).

9 If the matceach MOSF drains are diffin turn, influenally, since theL1 rings withand the voltadrain-to-sourcand minimizi tions in Paect both gatesuse an oscillavoltage and wQ1 VDcurrent with Diffmum drain voching circuits FET, the maferent, the twonces the mage drain induch the Coss of age spike on e voltage andng parasitic caralleled Ms and both dation on the gwind up damaDS Q2 VDS Q1 currentfferent Drain ltage as deteconsist of thex drain voltao excessive vgnitude of thectance of Q1 the AOT470 the drain dud cause failurcircuit inductaMOSFET Aprains togethegate. Worst caging the MOInductancesermined by thee same di/dt age seen by voltages cause di/dt and eveis larger, its and the parauring turn-off re. By carefuance during Ppplicationser when paralcase, the oscOSFET. Ringing Ps e parasitic indcharacteristiceach devicesed by the V =entually will reringing amplasitic resistancan easily mully designing PCB layout, ths lleling two MOcillation ampli age 4 of 8 ductance c and the e will be = L * di/dt esult in a itude (as nce in the make the the gate he circuit OSFETs.)

10 Itude can Rev. Example Figur Figure 5 shotogether. Thoscillations ovoltage or draThrough the result of addidentical on twhen paralle Root CaTo understanconnected toMOSFETs wThese compoResonanQuality faon Note Mes of OscillaFigurre 6. Turn-Ofows a clear ehe high frequeoften have veain-to-sourceuse of individding a single the two MOSled. This greause Analysisnd the causeogether, it iswith the parasonents form ant frequency oactor of a seriMOS-010 tion re 5. Turn-Offf Waveformsexample of aency oscillatioery high amp voltage and dual gate drivresistor in tFETs, meanieatly improvess of Gate Ose of the highs important tositic drain inda low-impedanof a series RLies RLC circuwwwff Waveformss of Two MOan oscillation on of ~150 MHplitudes and damage the dving resistorshe gate of eng that the cus the reliabilityscillation h frequency o analyze thductances, gnce loop and LC circuit fuit RLQ0 of Two MOSFETs Paralthat can occHz occurs ducan easily edevice.