PF3000, Power Management Integrated Circuit (PMIC) for i ...

1 * This document contains certain information on a new product. Specifications and information herein are subject to change without Number: PF3000 Rev. , 8/2017 NXP Semiconductors Data sheet: Advance Information NXP Management Integrated Circuit (PMIC) for 7 & 6SL/SX/ULThe PF3000 is a Power Management Integrated Circuit (PMIC) designed specifically for use with the NXP 7 and 6SL/SX/UL application processors. With up to four buck converters, six linear regulators, RTC supply, and coin-cell charger, the PF3000 can provide Power for a complete system, including applications processors, memory, and system peripherals. This device is powered by SMARTMOS : Four adjustable high efficiency buck regulators: A, A, A, A Selectable modes: PWM, PFM, APS V, 600 mA boost regulator with PFM or auto mode Six adjustable general purpose linear regulators Input voltage range: V to V or V to V OTP (One Time Programmable) memory for device configuration Programmable start-up sequence and timing Selectable output voltage, frequency, soft start I2C control Coin cell charger and always ON RTC supply DDR reference voltage -40 C to +125 C operating junction temperatureFigure 1.

2 PF3000 Simplified Application DiagramPOWER MANAGEMENTPF3000 Applications: Tablets eReaders Wearables POS terminals Industrial control Medical monitoring Home automation Home security/energy managementEP SUFFIX98 ASA00719D48 QFN X SUFFIX98 ASA00933D48 QFN X AMPM icrophonesSpeakersFront USB PODRear USB PODRear Seat CELL ChargerCOINCELLMain VGPSMIPIuPCIeCameraVREFDDRDDR MemorySD-MMC/NAND HDDWAMGPS/MIPIHDMILDVS to V @ to V, , @ to V @ to V @ Aor to V @ to V @ ASwitching to V@250 to V@ 100 mAVCC_SD to V @ 100 mAor to V @ 100 - V @ 350 - V @ 100 - V @ 350 mA RESETBMCUPWRONSD_VSELSTANDBYL inear regulatorsParallel control/GPIOSINTBP rocessor SOCP rocessor ARM CoreDDR MEMORY INTERFACESATA - FLASHNAND - NORI nterfaces 2 NXP SemiconductorsPF3000 Table of Contents1 Orderable parts.

3 32 General description .. 43 Internal block diagram .. 64 Pin connections .. Pinout diagram .. Pin definitions .. 85 General product characteristics .. Absolute maximum ratings .. Thermal Characteristics .. Current consumption .. Electrical characteristics .. 136 Functional description and application information .. Features .. 46 Functional description and application information .. Introduction .. Power generation .. Functional description .. Control logic and interface signals .. One-time-programmable memory .. 16 MHz and 32 kHz clocks .. Optional front-end input LDO regulator.. Internal core voltages .. VREFDDR voltage reference .. Buck regulators .. Boost regulator .. LDO Regulators Description.

4 VSNVS LDO/switch .. Power dissipation .. Modes of operation .. State diagram .. State machine flow summary .. Performance characteristics curves .. Control Interface I2C block description .. I2C device ID .. I2C operation .. Interrupt handling .. Interrupt bit summary .. Specific registers.. Register map..1027 Typical applications .. Application diagram .. 1108 Bill of materials .. 1119 Thermal information .. Rating data .. Estimation of junction temperature .. 11410 Packaging .. dimensions .. 11511 Revision history .. 121 ORDERABLE PARTS NXP Semiconductors3PF30001 Orderable partsThe PF3000 is available with pre-programmed OTP memory configurations. The devices are identified using the program codes from Ta b l e 1.

5 Details of the OTP programming for each device can be found in Table 42. Table 1. Orderable part variationsPart number Temperature (TA)PackageProgramming optionsNotesMC32PF3000A0EP-40 C to 85 C(For use in Consumer applications)98 ASA00719D, 48 QFN mm x mm with exposed pad0 - Not programmed(1), (2)MC32PF3000A1EP1 ( 7 with DDR3L)MC32PF3000A2EP2 ( 7 with LPDDR3)MC32PF3000A3EP3 ( 6SX with DDR3L)MC32PF3000A4EP4 ( 6SX with DDR3)MC32PF3000A5EP5 ( 6SL with LPDDR2)MC32PF3000A6EP6 ( 6UL with LPDDR2)MC32PF3000A7EP7 ( 6UL with DDR3L)MC32PF3000A8EP8 ( 6UL with DDR3)MC33PF3000A0ES-40 C to 105 C(For use in Automotive applications)98 ASA00933D, 48 QFN mm x mm WF-type (wettable flank)0 - Not programmed(1), (2)MC33PF3000A3ES3 ( 6SX with DDR3L)MC33PF3000A4ES4 ( 6SX with DDR3)MC33PF3000A5ES5 ( 6SL with LPDDR2)MC33PF3000A6ES6 ( 6UL with LPDDR2)MC33PF3000A7ES7 ( 6UL with DDR3L)

6 MC34PF3000A0EP-40 C to 105 C(For use in Industrial applications)98 ASA00719D, 48 QFN mm x mm with exposed pad0 - Not programmed(1), (2)MC34PF3000A1EP1 ( 7 with DDR3L)MC34PF3000A2EP2 ( 7 with LPDDR3)MC34PF3000A3EP3 ( 6SX with DDR3L)MC34PF3000A4EP4 ( 6SX with DDR3)MC34PF3000A5EP5 ( 6SL with LPDDR2)MC34PF3000A6EP6 ( 6UL with LPDDR2)MC34PF3000A7EP7 ( 6UL with DDR3L)MC34PF3000A8EP8 ( 6UL with DDR3) tape and reel, add an R2 suffix to the part programming options specified in this table are reference for customer application. The part number selection should match the board Power tree design. Table 42 provides details of the OTP programming for each DESCRIPTION 4 NXP SemiconductorsPF30002 General descriptionThe PF3000 is the Power Management Integrated Circuit (PMIC) designed primarily for use with NXP s 7 series of multi-media application processors.

7 It is also capable of providing full Power solution to 6SL/SX/UL This section summarizes the PF3000 features. Input voltage range to PMIC: V to V, or V to V (3) Buck regulators Configurable three to four channels SW1A/B, A (single); V to V, V, V SW1A, A (independent); V to V, V, V SW1B A (independent); V to V SW2, A; V to V or V to V SW3, A; V to V Dynamic voltage scaling Modes: PWM, PFM, APS Programmable output voltage Programmable current limit Programmable soft start sequence Programmable PWM switching frequency Boost regulator SWBST, to V, A, OTG support Modes: PFM and Auto OCP fault interrupt LDOs VCC_SD, V to V or V to V, 100 mA based on SD_VSEL V33, V to V, 350 mA VLDO1, V to V, 100 mA VLDO2, V to V, 250 mA VLDO3, V to V, 100 mA VLDO4, V to V, 350 mA Always ON RTC Regulator/Switch VSNVS V, mA DDR memory reference voltage, VREFDDR, V to V, 10 mA OTP (One time programmable) memory for device configuration, user-programmable start-up sequence and timing Battery backed memory including coin cell charger I2C interface User programmable standby, sleep/LPSR, and Off V to V when VIN is used at input.

8 V to V when VPWR is used as input. GENERAL DESCRIPTION NXP block diagramFigure 2. Functional block diagramLogic and controlSwitching regulatorsSW1A( V to V, V, V, A)Linear regulatorsSW2( V to V, A) or ( V to V, A)SW3( V to V, A)Boost regulator( V to V, 600 mA)USB OTG SupplyVLDO1( V to V, 100 mA)VLDO2( V to V, 250 mA)VCC_SD( V or V, 100 mA)or ( V or V, 100 mA)V33( V to V, 350 mA)VLDO3( V to V, 100 mA)VLDO4( V to V, 350 mA)Bias & referencesParallel MCU interfaceRegulator controlVSNVS( V to V, mA)RTC supply with coin cell chargerPF3000 functional internal block diagramI2C communication & registersPower generationFault detection and protectionDDR voltage referenceCurrent limitVPWR front end LDO overvoltage indicatorInternal core voltage referenceThermal OTP startup configurationSequence and timingOTP prototyping (Try before burn)

9 VoltagePhasing and frequency selectionSW1B( V to V , A)INTERNAL BLOCK DIAGRAM 6 NXP SemiconductorsPF30003 Internal block diagram Figure 3. PF3000 simplified internal block diagramVININTBLICELLSWBSTFBSWBSTLXO/PDri veSWBST600 mABoostPWRONSTANDBYICTESTSCLSDAVDDIOSW3 ABuckVCOREDIGVCOREREFSD_VSELGNDREFSW1 AINSW1 AFBSW1 ALXSW1 BLXSW1A A BuckVSNVSVSNVSLi Cell ChargerRESETBMCUSW2 A BuckVLDO1 100 mAVLDO1 VLDO1 INVLDO2 250 V 350 mAV33 VLDO3 100 mAVLDO3 VLDO34 INVLDO4 350 mAVLDO4 Best of SupplyOTPVREFDDRVDDOTPVINREFDDRVHALFVCOR EPF3000 CONTROLC locks32 kHz and 16 MHzInitialization State MachineI2C InterfaceClocks and resetsI2C Register mapTrim-In-PackageO/PDriveO/PDriveSW1 BINSW2 FBSW2 LXO/PDriveSW2 INSW3 INSW3 FBSW3 LXO/PDriveGNDREF2 Supplies ControlDVS ControlDVS CONTROLR eference GenerationCore Control logicGNDREF2 GNDREF1SW1B A 100 mAPIN CONNECTIONS NXP Semiconductors7PF30004 Pin diagramFigure 4.

10 Pinout diagramINTBSD_VSELRESETBMCUSTANDBYICTEST SW1 AFBSW1 AINSW1 ALXSW1 BLXSW1 BINSW1 BFBGNDREF1 VLDO1 INVLDO1 VLDO2 VLDO2 INSW2 LXSW2 INSW2 FBVLDO3 VLDO34 INVLDO4 VHALFVINREFDDRPWRONVDDIOSCLSDAVCOREREFVC OREDIGVINVCOREGNDREFVDDOTPVIN2 SWBSTFBLICELLSWBSTLXVSNVSVCC_SDV33 VPWRLDOGSW3 LXSW3 INSW3 FBGNDREF2 VREFDDR123456789101112131415161718192021 2223243635343332313029282726254847464544 43424140393837 EPTransparent Top ViewPIN CONNECTIONS 8 NXP definitionsTable 2. Pin definitions Pin numberPin namePin functionTypeDefinition1 INTBOD igitalOpen drain interrupt signal to processor2SD_VSELI/ODigitalInput from processor to select VCC_SD regulator voltage SD_VSEL=0, VCC_SD = V to V SD_VSEL= 1, VCC_SD = V to V3 RESETBMCUOD igitalOpen drain reset output to processor4 STANDBYID igitalStandby input signal from processor5 ICTESTID igital and AnalogReserved pin.