1024Bytes EEPROM 8-bit Microcontroller with 32KBytes In ...

1 Features High-performance, Low-power Atmel AVR 8-bit Microcontroller Advanced RISC Architecture 131 Powerful Instructions Most Single-clock Cycle Execution 32 8 General Purpose Working Registers Fully Static Operation Up to 16 MIPS Throughput at 16 MHz On-chip 2-cycle Multiplier High Endurance Non-volatile Memory segments 32 Kbytes of In-System Self-programmable Flash program memory 1024 Bytes EEPROM . 2 Kbytes Internal SRAM. 8-bit Write/Erase Cycles: 10,000 Flash/100,000 EEPROM . Data retention: 20 years at 85 C/100 years at 25 C(1). Microcontroller Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program with 32 KBytes True Read-While-Write Operation Programming Lock for Software Security In-System JTAG (IEEE std.)

2 Compliant) Interface Boundary-scan Capabilities According to the JTAG Standard Programmable Extensive On-chip Debug Support . Programming of Flash, EEPROM , Fuses, and Lock Bits through the JTAG Interface Peripheral Features Flash Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode Real Time Counter with Separate Oscillator ATmega32. Four PWM Channels 8-channel, 10-bit ADC. ATmega32L. 8 Single-ended Channels 7 Differential Channels in TQFP Package Only 2 Differential Channels with Programmable Gain at 1x, 10x, or 200x Byte-oriented Two-wire Serial Interface Programmable Serial USART.

3 Master/Slave SPI Serial Interface Programmable Watchdog Timer with Separate On-chip Oscillator On-chip Analog Comparator Special Microcontroller Features Power-on Reset and Programmable Brown-out Detection Internal Calibrated RC Oscillator External and Internal Interrupt Sources Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby I/O and Packages 32 Programmable I/O Lines 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF. Operating Voltages - for ATmega32L. - for ATmega32. Speed Grades 0 - 8 MHz for ATmega32L. 0 - 16 MHz for ATmega32. Power Consumption at 1 MHz, 3V, 25 C.

4 Active: Idle Mode: Power-down Mode: < 1 A. 2503Q AVR 02/11. ATmega32(L). Pin Configurations Figure 1. Pinout ATmega32. PDIP. (XCK/T0) PB0 PA0 (ADC0). (T1) PB1 PA1 (ADC1). (INT2/AIN0) PB2 PA2 (ADC2). (OC0/AIN1) PB3 PA3 (ADC3). (SS) PB4 PA4 (ADC4). (MOSI) PB5 PA5 (ADC5). (MISO) PB6 PA6 (ADC6). (SCK) PB7 PA7 (ADC7). RESET AREF. VCC GND. GND AVCC. XTAL2 PC7 (TOSC2). XTAL1 PC6 (TOSC1). (RXD) PD0 PC5 (TDI). (TXD) PD1 PC4 (TDO). (INT0) PD2 PC3 (TMS). (INT1) PD3 PC2 (TCK). (OC1B) PD4 PC1 (SDA). (OC1A) PD5 PC0 (SCL). (ICP1) PD6 PD7 (OC2). TQFP/MLF. PB2 (AIN0/INT2). PB3 (AIN1/OC0). PB0 (XCK/T0). PA0 (ADC0).

5 PA1 (ADC1). PA2 (ADC2). PA3 (ADC3). PB4 (SS). PB1 (T1). GND. VCC. (MOSI) PB5 PA4 (ADC4). (MISO) PB6 PA5 (ADC5). (SCK) PB7 PA6 (ADC6). RESET PA7 (ADC7). VCC AREF. GND GND. XTAL2 AVCC. XTAL1 PC7 (TOSC2). (RXD) PD0 PC6 (TOSC1). (TXD) PD1 PC5 (TDI). (INT0) PD2 PC4 (TDO). PD3. PD4. PD5. PD6. PD7. VCC. GND. (SCL) PC0. (SDA) PC1. (TCK) PC2. (TMS) PC3. Note: Bottom pad should (INT1). (OC1B). (OC1A). (ICP1). (OC2). be soldered to ground. 2. 2503Q AVR 02/11. ATmega32(L). Overview The Atmel AVR ATmega32 is a low-power CMOS 8-bit Microcontroller based on the AVR. enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega32 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

6 Block Diagram Figure 2. Block Diagram PA0 - PA7 PC0 - PC7. VCC. PORTA DRIVERS/BUFFERS PORTC DRIVERS/BUFFERS. GND PORTA DIGITAL INTERFACE PORTC DIGITAL INTERFACE. AVCC. MUX & ADC. TWI. INTERFACE. ADC. AREF. TIMERS/. PROGRAM STACK OSCILLATOR. COUNTERS. COUNTER POINTER. PROGRAM INTERNAL. SRAM. FLASH OSCILLATOR. XTAL1. INSTRUCTION GENERAL WATCHDOG. OSCILLATOR. REGISTER PURPOSE TIMER. REGISTERS. XTAL2. X. INSTRUCTION MCU CTRL. Y RESET. DECODER & TIMING. Z. INTERNAL. CONTROL INTERRUPT. CALIBRATED. LINES ALU UNIT. OSCILLATOR. STATUS. AVR CPU REGISTER. EEPROM . PROGRAMMING. LOGIC. SPI USART. + COMP. - INTERFACE.

7 PORTB DIGITAL INTERFACE PORTD DIGITAL INTERFACE. PORTB DRIVERS/BUFFERS PORTD DRIVERS/BUFFERS. PB0 - PB7 PD0 - PD7. 3. 2503Q AVR 02/11. ATmega32(L). The Atmel AVR AVR core combines a rich instruction set with 32 general purpose working reg- isters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers . The ATmega32 provides the following features: 32 Kbytes of In-System Programmable Flash Program memory with Read-While-Write capabilities, 1024Bytes EEPROM , 2 Kbyte SRAM, 32.

8 General purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary- scan, On-chip Debugging support and programming, three flexible Timer/Counters with com- pare modes, Internal and External Interrupts, a serial programmable USART, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable gain (TQFP package only), a programmable Watchdog Timer with Internal Oscil- lator, an SPI serial port, and six software selectable power saving modes. The Idle mode stops the CPU while allowing the USART, Two-wire interface, A/D Converter, SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning.

9 The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next External Inter- rupt or Hardware Reset. In Power-save mode, the Asynchronous Timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC. Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/reso- nator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption.

10 In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. The device is manufactured using Atmel's high density nonvolatile memory technology. The On- chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation.