24AA01/24LC01B 1K I2C Serial EEPROM Data Sheet

1 2009 Microchip Technology 124AA01/24LC01 BDevice Selection TableFeatures: Single Supply with Operation down to for 24 AAXX Devices, for 24 LCXX Devices Low-Power CMOS Technology:- Read current 1 mA, Standby current 1 A, max. (I-temp) 2-Wire Serial Interface, I2C Compatible Schmitt Trigger inputs for Noise Suppression Output Slope Control to eliminate Ground Bounce 100 kHz and 400 kHz Compatibility Page Write Time 3 ms, typical Hardware Write-Protect ESD Protection >4,000V More than 1 Million Erase/Write Cycles data Retention >200 Years Factory Programmable Available Packages include 8-lead PDIP, SOIC, TSSOP, DFN, TDFN, MSOP, 5-lead SOT-23 and SC-70 Pb-free and RoHS Compliant Temperature Ranges:- Industrial (I): -40 C to +85 C- Automotive (E): -40 C to +125 CDescription:The Microchip Technology Inc.

2 24AA01/24LC01B (24XX01*) is a 1 Kbit Electrically Erasable PROM. Thedevice is organized as one block of 128 x 8-bit memorywith a 2-wire Serial interface. Low-voltage designpermits operation down to with standby and activecurrents of only 1 A and 1 mA, respectively. The24XX01 also has a page write capability for up to 8bytes of data . The 24XX01 is available in the standard8-pin PDIP, surface mount SOIC, TSSOP, 2x3 DFN,2x3 TDFN and MSOP packages, and is also availablein the 5-lead SOT-23 and SC-70 TypesBlock DiagramPart NumberVCCR angeMax. Clock FrequencyTemp. kHz(1) kHzI, ENote 1:100 kHz for VCC < , MSOPSOIC, TSSOPA0A1A2 VSS12348765 VCCWPSCLSDADFN/TDFNA0A1A2 VSSWPSCLSDAVCCSOT-23/SC-701543 SCLVssSDAWPVcc2 Note:Pins A0, A1 and A2 are not used by the 24XX01 (nointernal connections).

3 87651234HV GeneratorEEPROM ArrayPage LatchesYDECXDECS ense Control1K I2C Serial EEPROM24AA01/24LC01 BDS21711J-page 2 2009 Microchip Technology CHARACTERISTICSA bsolute Maximum Ratings ( ) inputs and outputs to VCC + temperature ..-65 C to +150 CAmbient temperature with power applied ..-40 C to +125 CESD protection on all 4kVTABLE 1-1:DC CHARACTERISTICS NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage tothe device. This is a stress rating only and functional operation of the device at those or any other conditionsabove those indicated in the operational listings of this specification is not implied. Exposure to maximum ratingconditions for extended periods may affect device CHARACTERISTICSI ndustrial (I):TA = -40 C to +85 C, VCC = + to + (E): TA = -40 C to +125 C, VCC = + to + , SCL and SDA pins D2 High-level input VCC V D3 VILLow-level input voltage VCCV D4 VHYSH ysteresis of SchmittTrigger VCC V(Note)D5 VOLLow-level output voltage = mA, VCC = leakage current 1 AVIN = VSS or VCCD7 ILOO utput leakage current 1 AVOUT = VSS or VCCD8 CIN, COUTPin capacitance(all inputs/outputs) 10pFVCC = (Note)TA = 25 C, FCLK = 1 MHzD9 ICC writeOperating current 3mAVCC = , SCL = 400 kHzD10 ICC read D11 ICCSS tandby current 15 IndustrialAutomotiveSDA = SCL = VCCWP = VSSNote:This parameter is periodically sampled and not 100% tested.

4 2009 Microchip Technology 324AA01/24LC01 BTABLE 1-2:AC CHARACTERISTICSAC CHARACTERISTICSI ndustrial (I):TA = -40 C to +85 C, VCC = + to + (E): TA = -40 C to +125 C, VCC = + to + frequency VCC VCC < (24AA01)2 THIGHC lock high time6004000 VCC VCC < (24AA01)3 TLOWC lock low time13004700 VCC VCC < (24AA01)4 TRSDA and SCL rise time (Note 1) VCC VCC < (24AA01) 5 TFSDA and SCL fall time 300ns(Note 1)6 THD:STAS tart condition hold time6004000 VCC VCC < (24AA01)7 TSU:STAS tart condition setup time6004700 VCC VCC < (24AA01)8 THD:DATData input hold time0 ns(Note 2)9 TSU:DATData input setup time100250 VCC VCC < (24AA01)10 TSU:STOStop condition setup time6004000 VCC VCC < (24AA01)11 TAAO utput valid from clock (Note 2) VCC VCC < (24AA01)12 TBUFBus free-time: Time the bus must be free before a new transmission can start13004700 VCC VCC < (24AA01)13 TOFO utput fall time from VIH minimum to VIL maximum20+ VCC VCC < (24AA01)14 TSPI nput filter spike suppression(SDA and SCL pins) 50ns(Notes 1 and 3)15 TWCW rite cycle time (byte or page) 5ms 16 Endurance1M cycles 25 C, (Note 4)Note 1:Not 100% tested.

5 CB = total capacitance of one bus line in :As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop :The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard :This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained from Microchip s web site at 4 2009 Microchip Technology 1-1:BUS TIMING DATAFIGURE 1-2:BUS TIMING START/STOP752489101211146 SCLSDAINSDAOUT376D410 StartStopSCLSDA 2009 Microchip Technology 524AA01 DESCRIPTIONSThe descriptions of the pins are listed in Table 2-1:PIN FUNCTION , A1, A2 The A0, A1 and A2 pins are not used by the may be left floating or tied to either VSS or Address/ data Input/Output (SDA)The SDA input is a bidirectional pin used to transferaddresses and data into and out of the device.

6 Sinceit is an open-drain terminal, the SDA bus requires apull-up resistor to VCC (typical 10 k for 100 kHz,2k for 400 kHz).For normal data transfer, SDA is allowed to changeonly during SCL low. Changes during SCL high arereserved for indicating Start and Stop Clock (SCL)The SCL input is used to synchronize the data transferto and from the (WP)This pin must be connected to either VSS or tied to VSS, normal memory operation is enabled(read/write the entire memory 00-7F).If tied to VCC, write operations are inhibited. The entirememory will be write-protected. Read operations arenot Not ConnectedA1222222 Not ConnectedA2333333 Not ConnectedVSS44444422 GroundSDA55555533 Serial Address/ data I/OSCL66666611 Serial ClockWP77777755 Write-Protect InputVCC88888844+ to Power Supply24AA01/24LC01 BDS21711J-page 6 2009 Microchip Technology DESCRIPTIONThe 24XX01 supports a bidirectional, 2-wire bus anddata transmission protocol.

7 A device that sends dataonto the bus is defined as transmitter, while defining adevice receiving data as a receiver. The bus has to becontrolled by a master device which generates theSerial Clock (SCL), controls the bus access andgenerates the Start and Stop conditions, while the24XX01 works as slave. Both master and slave canoperate as transmitter or receiver, but the masterdevice determines which mode is CHARACTERISTICSThe following bus protocol has been defined: data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop , the following bus conditions have beendefined (Figure 4-1).

8 Not Busy (A)Both data and clock lines remain data Transfer (B)A high-to-low transition of the SDA line while the clock(SCL) is high determines a Start condition. Allcommands must be preceded by a Start data Transfer (C)A low-to-high transition of the SDA line while the clock(SCL) is high determines a Stop condition. Alloperations must be ended with a Stop Valid (D)The state of the data line represents valid data when,after a Start condition, the data line is stable for theduration of the high period of the clock data on the line must be changed during the lowperiod of the clock signal. There is one clock pulse perbit of data transfer is initiated with a Start condition andterminated with a Stop condition. The number of databytes transferred between the Start and Stopconditions is determined by the master device and is,theoretically, unlimited (although only the last sixteenwill be stored when doing a write operation).

9 When anoverwrite does occur, it will replace data in a first-infirst-out (FIFO) receiving device, when addressed, is obliged togenerate an acknowledge after the reception of eachbyte. The master device must generate an extra clockpulse which is associated with this Acknowledge device that acknowledges has to pull down theSDA line during the acknowledge clock pulse in such away that the SDA line is stable-low during the highperiod of the acknowledge-related clock pulse. Ofcourse, setup and hold times must be taken intoaccount. During reads, a master must signal an end ofdata to the slave by not generating an Acknowledge biton the last byte that has been clocked out of the this case, the slave (24XX01) will leave the data linehigh to enable the master to generate the 4-1: data TRANSFER SEQUENCE ON THE Serial BUSNote:The 24XX01 does not generate anyAcknowledge bits if an internalprogramming cycle is in (A)(B)(D)(D)(A)(C)StartConditionAddress orAcknowledgeValidDataAllowedto ChangeStopCondition 2009 Microchip Technology 724AA01 ADDRESSINGA control byte is the first byte received following theStart condition from the master device.

10 The control byteconsists of a four-bit control code. For the 24XX01, thisis set as 1010 binary for read and write next three bits of the control byte are don t cares for the last bit of the control byte defines the operation tobe performed. When set to 1 , a read operation isselected. When set to 0 , a write operation is the Start condition, the 24XX01 monitors theSDA bus, checking the device type identifier beingtransmitted. Upon receiving a 1010 code, the slavedevice outputs an Acknowledge signal on the SDA on the state of the R/W bit, the 24XX01 willselect a read or write 5-1:CONTROL BYTE ALLOCATION FIGURE 5-2:ADDRESS SEQUENCE BIT ASSIGNMENTSO perationControl CodeBlock SelectR/WRead1010 Block Address1 Write1010 Block Address01010xxxR/WACKS tart BitRead/Write Bitx = don t care SSlave AddressAcknowledge BitControl CodeBlockSelect Bits1010xxR/WA6A0 Control ByteAddress Low ByteControlCodeBlockSelectbitsx = don t care xx24AA01/24LC01 BDS21711J-page 8 2009 Microchip Technology WriteFollowing the Start condition from the master, thedevice code (4 bits), the block address (3 bits, don tcares ) and the R/W bit, which is a logic-low, is placedonto the bus by the master transmitter.