24AA16/LC16B Data Sheet - Microchip Technology

1 2002-2012 Microchip Technology 124AA16/24LC16 BDevice Selection TableFeatures: Single Supply with Operation down to 24aa16 Devices, for 24LC16B Devices Low-Power CMOS Technology :- Active current 1 mA, typical- Standby current, 1 A, typical 2-Wire Serial Interface, I2C Compatible Schmitt Trigger inputs for Noise Suppression Output Slope Control to eliminate Ground Bounce 100 kHz and 400 kHz Clock Compatibility Page Write Time 5 ms Max. Self-Timed Erase/Write Cycle 16-Byte Page Write Buffer Hardware Write-Protect ESD Protection > 4,000V More than 1 Million Erase/Write Cycles Data Retention > 200 Years Factory Programming Available Packages include 8-lead PDIP, SOIC, TSSOP, MSOP, DFN, TDFN, 5-lead SOT-23 and Chip Scale Pb-Free and RoHS Compliant Temperature Ranges:- Industrial (I): -40 C to +85 C- Automotive (E): -40 C to +125 CDescription:The Microchip Technology Inc.

2 24aa16 /24LC16B(24XX16*) is a 16 Kbit Electrically Erasable device is organized as eight blocks of 256 x 8-bitmemory with a 2-wire serial interface. Low-voltagedesign permits operation down to with standbyand active currents of only 1 A and 1 mA,respectively. The 24XX16 also has a page writecapability for up to 16 bytes of data. The 24XX16 isavailable in the standard 8-pin PDIP, surface mountSOIC, TSSOP, 2x3 DFN, 2x3 TDFN and MSOP pack-ages, and is also available in the 5-lead SOT-23, andChip Scale DiagramPart NumberVCC RangeMax. Clock FrequencyTemp. kHz(1)I, kHzI, ENote 1:100 kHz for VCC < EEPROM ArrayPage YDECXDECS ense ControlLatchesGeneratorA0A1A2 VSSVCCWPSCLSDA12348765 PDIP/MSOP/SOIC/TSSOPDFN/TDFNA0A1A2 VSSWPSCLSDAVCC87651234 SOT-2312345 WPVCCSCLVSSSDANote 1:Pins A0, A1 and A2 are not used by the 24XX16 (no internal connections).

3 2:Available in I-temp, AA (Chip Scale)(1)12345 VCCWPSDASCLVSS(Top Down View,Balls Not Visible)16K I2C Serial EEPROM*24XX16 is used in this document as a generic part number for the 24aa16 /24LC16B 2 2002-2012 Microchip Technology CHARACTERISTICSA bsolute Maximum Ratings ( ) inputs and outputs to VCC + temperature ..-65 C to +150 CAmbient temperature with power applied ..-40 C to +125 CESD protection on all pins 4kVTABLE 1-1:DC CHARACTERISTICS NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to thedevice. This is a stress rating only and functional operation of the device at those or any other conditions above thoseindicated in the operational listings of this specification is not implied.

4 Exposure to maximum rating conditions forextended periods may affect device CHARACTERISTICSI ndustrial (I): TA = -40 C to +85 C, VCC = + to + (E): TA = -40 C to +125 C, VCC = + to + , SCL and SDA pins D1 VIHHigh-level input VCC V D2 VILLow-level input voltage VCCV D3 VHYSH ysteresis of SchmittTrigger VCC V(Note 1)D4 VOLLow-level output voltage = mA, VCC = leakage current 1 AVIN = VSS or VCCD6 ILOO utput leakage current 1 AVOUT = VSS or VCCD7 CIN, COUTPin capacitance(all inputs/outputs) 10pFVCC = (Note 1)TA = 25 C, FCLK = 1 MHzD8 ICC writeOperating current 3mAVCC = , SCL = 400 kHzD9 ICC read D10 ICCSS tandby current A AIndustrialAutomotiveSDA = SCL = VCCWP = VSSNote 1:This parameter is periodically sampled and not 100% :Typical measurements taken at room temperature.

5 2002-2012 Microchip Technology 324AA16/24LC16 BTABLE 1-2:AC CHARACTERISTICSAC CHARACTERISTICSI ndustrial (I): TA = -40 C to +85 C, VCC = + to + (E): TA = -40 C to +125 C, VCC = + to + frequency VCC VCC ( 24aa16 )2 THIGHC lock high time6004000 VCC VCC ( 24aa16 )3 TLOWC lock low time13004700 VCC VCC ( 24aa16 )4 TRSDA and SCL rise time (Note 1) VCC (Note 1) VCC ( 24aa16 ) (Note 1)5 TFSDA and SCL fall time 300ns(Note 1)6 THD:STAS tart condition hold time6004000 VCC VCC ( 24aa16 )7 TSU:STAS tart condition setup time6004700 VCC VCC ( 24aa16 )8 THD:DATData input hold time0 ns(Note 2)9 TSU:DATData input setup time100250 VCC VCC ( 24aa16 )10 TSU:STOStop condition setup time6004000 VCC VCC ( 24aa16 )11 TAAO utput valid from clock (Note 2) VCC VCC ( 24aa16 )12 TBUFBus free time: Time the bus must be free before a new transmission can start13004700 VCC VCC ( 24aa16 )13 TOFO utput fall time from VIH minimum to VIL maximum20+ VCC VCC ( 24aa16 )14 TSPI nput filter spike suppression(SDA and SCL pins) 50ns(Notes 1 and3)15 TWCW rite cycle time (byte or page) 5ms 16 Endurance1M cycles 25 C, (Note 4)Note 1:Not 100% tested.

6 CB = total capacitance of one bus line in :As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop :The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard :This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained from Microchip s web site at 4 2002-2012 Microchip Technology 1-1:BUS TIMING DATAFIGURE 1-2:BUS TIMING START/STOP752489101211146 SCLSDAINSDAOUT376D310 StartStopSCLSDA 2002-2012 Microchip Technology 524AA16 DESCRIPTIONSThe descriptions of the pins are listed in Ta b l e 2 - 2-1:PIN FUNCTION Address/Data Input/Output (SDA)SDA is a bidirectional pin used to transfer addressesand data into and out of the device.

7 Since it is an open-drain terminal, the SDA bus requires a pull-up resistorto VCC (typical 10 k for 100 kHz, 2 k for 400 kHz).For normal data transfer, SDA is allowed to changeonly during SCL low. Changes during SCL high arereserved for indicating Start and Stop Clock (SCL)The SCL input is used to synchronize the data transferto and from the (WP) The WP pin must be connected to either VSS or tied to VSS, normal memory operation is enabled(read/write the entire memory 000-7FF).If tied to VCC, write operations are inhibited. The entirememory will be write-protected. Read operations arenot , A1, A2 The A0, A1 and A2 pins are not used by the may be left floating or tied to either VSS or Not ConnectedA1222222 Not ConnectedA2333333 Not ConnectedVSS44444422 GroundSDA55555535 Serial Address/Data I/OSCL66666614 Serial ClockWP77777753 Write-Protect InputVCC88888841+ to Power Supply24AA16/24LC16 BDS21703L-page 6 2002-2012 Microchip Technology DESCRIPTIONThe 24XX16 supports a bidirectional, 2-wire bus anddata transmission protocol.

8 A device that sends dataonto the bus is defined as a transmitter, while a devicereceiving data is defined as a receiver. The bus has tobe controlled by a master device which generates theSerial Clock (SCL), controls the bus access andgenerates the Start and Stop conditions, while the24XX16 works as slave. Both master and slave canoperate as transmitter or receiver, but the masterdevice determines which mode is CHARACTERISTICSThe following bus protocol has been defined: Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop , the following bus conditions have beendefined (Figure 4-1).

9 Not Busy (A)Both data and clock lines remain Data Transfer (B)A high-to-low transition of the SDA line while the clock(SCL) is high determines a Start condition. Allcommands must be preceded by a Start Data Transfer (C)A low-to-high transition of the SDA line while the clock(SCL) is high determines a Stop condition. Alloperations must be ended with a Stop Valid (D)The state of the data line represents valid data when,after a Start condition, the data line is stable for theduration of the high period of the clock data on the line must be changed during the lowperiod of the clock signal. There is one clock pulse perbit of data transfer is initiated with a Start condition andterminated with a Stop condition.

10 The number of databytes transferred between Start and Stop conditions isdetermined by the master device and is, theoretically,unlimited (although only the last sixteen will be storedwhen doing a write operation). When an overwrite doesoccur it will replace data in a first-in first-out (FIFO) receiving device, when addressed, is obliged togenerate an Acknowledge after the reception of eachbyte. The master device must generate an extra clockpulse which is associated with this Acknowledge bit. The device that acknowledges, has to pull down theSDA line during the acknowledge clock pulse in such away that the SDA line is stable-low during the highperiod of the acknowledge related clock pulse.