24AA256/LC/FC Data Sheet - Microchip Technology

1 1998-2013 Microchip Technology 124AA256/24LC256/24FC256 Device selection TableFeatures: Single Supply with Operation Down to for 24AA256 and 24FC256 Devices, for 24LC256 Devices Low-Power CMOS Technology :- Read current: 400 uA max. at , 400 kHz- Standby current: 1 uA max. at , I-temp 2-Wire Serial Interface, I2C Compatible Cascadable up to Eight Devices Schmitt Trigger Inputs for Noise Suppression Output Slope Control to Eliminate Ground Bounce 100 kHz and 400 kHz Clock Compatibility Page Write Time 5 ms Max. Self-Timed Erase/Write Cycle 64-Byte Page Write Buffer Hardware Write-Protect ESD Protection >4000V More than One Million Erase/Write Cycles data Retention >200 years Factory Programming Available Packages Include 8-lead PDIP, SOIC, SOIJ, DFN, TDFN, TSSOP and MSOP RoHS Compliant Temperature Ranges:Description:The Microchip Technology Inc.

2 24AA256/24LC256/24FC256 (24XX256*) is a 32K x 8 (256 Kbit) SerialElectrically Erasable PROM, capable of operationacross a broad voltage range ( to ). It hasbeen developed for advanced, low-power applicationssuch as personal communications or data device also has a page write capability of up to 64bytes of data . This device is capable of both randomand sequential reads up to the 256K address lines allow up to eight devices onthe same bus, for up to 2 Mbit address space. Thisdevice is available in the standard 8-pin plastic DIP,SOIC, SOIJ, TSSOP, MSOP, DFN and TDFN pack-ages.

3 The 24AA256 is also available in the 8-lead ChipScale DiagramPackage Types*24XX256 is used in this document as a generic part number for the 24AA256/24LC256/24FC256 NumberVCC RangeMax. ClockFrequencyTemp. kHz(1)I, kHzI, MHz(2)INote 1:100 kHz for VCC < :400 kHz for VCC < Industrial (I):-40 C to +85 C- Automotive (E): -40 C to +125 CHV GeneratorEEPROM ArrayPage LatchesYDECXDECS ense ControlMemoryControlLogicI/OControlLogic I/OA0 A1A2 SDASCLVCCVSSWPA0A1A2 VSSVCCWPSCLSDA1234876524XX256 PDIP/SOIC/SOIJTSSOP/MSOP(1)A0A1A2 VSS12348765 VCCWPSCLSDA24XX256 DFN/TDFNA0A1A2 VSSWPSCLSDA24XX25656784321 VCCNote 1: * Pins A0 and A1 are no connects for the MSOP package 2.

4 Available in I-temp, AA (Chip Scale)(2)12345678 VCCA1 A0 WPA2 SDA SCL VSS(TOP DOWN VIEW,BALLS NOT VISIBLE)256K I2C CMOS Serial EEPROM24AA256/24LC256/24FC256DS20001203U -page 2 1998-2013 Microchip Technology CHARACTERISTICSA bsolute Maximum Ratings( ) inputs and outputs to VCC + temperature ..-65 C to +150 CAmbient temperature with power applied ..-40 C to +125 CESD protection on all pins 4kVTABLE 1-1:DC CHARACTERISTICS NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to thedevice. This is a stress rating only and functional operation of the device at these or any other conditions above thoseindicated in the operational listings of this specification is not implied.

5 Exposure to Absolute Maximum Ratingconditions for extended periods may affect device CHARACTERISTICSE lectrical Characteristics:Industrial (I):VCC = + to = -40 C to +85 CAutomotive (E):VCC = + to = -40 C to +125 A0, A1, A2, SCL, SDA and WP pins: D1 VIHHigh-level input VCC V D2 VILLow-level input voltage VCCVVVCC < of Schmitt Trigger inputs(SDA, SCL pins) VCC VVCC (Note)D4 VOLLow-level output voltage = mA @ VCC = = mA @ VCC = leakage current 1 AVIN = VSS or VCC, WP = VSSVIN = VSS or VCC, WP = VCCD6 ILOO utput leakage current 1 AVOUT = VSS or VCCD7 CIN, COUTPin capacitance (all inputs/outputs) 10pFVCC = (Note)

6 TA = 25 C, FCLK = 1 MHzD8 ICC Read Operating current 400 AVCC = , SCL = 400 kHzICC Write 3mAVCC = current ATA = -40 C to +85 CSCL = SDA = VCC = , A1, A2, WP = VSS 1 ATA = -40 C to +85 CSCL = SDA = VCC = , A1, A2, WP = VSS 5 ATA = -40 C to +125 CSCL = SDA = VCC = , A1, A2, WP = VSSNote:This parameter is periodically sampled and not 100% tested. 1998-2013 Microchip Technology 324AA256/24LC256/24FC256 TABLE 1-2:AC CHARACTERISTICSAC CHARACTERISTICSE lectrical Characteristics:Industrial (I):VCC = + to = -40 C to +85 CAutomotive (E):VCC = + to = -40 C to +125 frequency VCC VCC VCC VCC 24FC2562 THIGHC lock high time4000600600500 VCC VCC VCC VCC 24FC2563 TLOWC lock low time470013001300500 VCC VCC VCC VCC 24FC2564 TRSDA and SCL rise time (Note 1) VCC VCC VCC 24FC2565 TFSDA and SCL fall time (Note 1) 300100nsAll except, VCC 24FC2566 THD:STAS tart condition hold time4000600600250 VCC VCC VCC VCC 24FC2567 TSU.

7 STAS tart condition setup time4700600600250 VCC VCC VCC VCC 24FC2568 THD:DATData input hold time0 ns(Note 2)9 TSU:DATData input setup time250100100 VCC VCC VCC 24FC25610 TSU:STOStop condition setup time4000600600250 VCC VCC VCC VCC 24FC25611 TSU:WPWP setup time4000600600 VCC VCC VCC 24FC25612 THD:WPWP hold time470013001300 VCC VCC VCC 24FC256 Note 1:Not 100% tested. CB = total capacitance of one bus line in :As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop :The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression.

8 This eliminates the need for a TI specification for standard :This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model, which can be obtained from Microchip s web site at 4 1998-2013 Microchip Technology 1-1:BUS TIMING DATA13 TAAO utput valid from clock (Note 2) V VCC V VCC VCC V VCC 24FC25614 TBUFBus free time: Time the bus must be free before a new transmission can start470013001300500 VCC VCC VCC VCC 24FC25615 TOFO utput fall time from VIHminimum to VIL maximumCB 100 pF 10 + except, 24FC256 (Note 1)16 TSPI nput filter spike suppression(SDA and SCL pins) 50nsAll except, 24FC256 (Notes 1 and3)17 TWCW rite cycle time (byte or page) 5ms 18 Endurance1,000,000 cycles Page mode, 25 C, (Note 4)AC CHARACTERISTICS (Continued)Electrical Characteristics:Industrial (I):VCC = + to = -40 C to +85 CAutomotive (E):VCC = + to = -40 C to +125 1:Not 100% tested.

9 CB = total capacitance of one bus line in :As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop :The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard :This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model, which can be obtained from Microchip s web site at (unprotected)(protected)SCLSDAINSDAOUTWP 57616328913D3410111214 1998-2013 Microchip Technology 524AA256/24LC256 DESCRIPTIONSThe descriptions of the pins are listed in Ta b l e 2 - 2-1:PIN FUNCTION , A1, A2 Chip Address InputsThe A0, A1 and A2 inputs are used by the 24XX256 formultiple device operations.

10 The levels on these inputsare compared with the corresponding bits in the slaveaddress. The chip is selected if the compare is the MSOP package only, pins A0 and A1 are to eight devices (two for the MSOP package) maybe connected to the same bus by using different ChipSelect bit combinations. These inputs must beconnected to either VCC or most applications, the chip address inputs A0, A1and A2 are hard-wired to logic 0 or logic 1 . Forapplications in which these pins are controlled by amicrocontroller or other programmable device, the chipaddress pins must be driven to logic 0 or logic 1 before normal device operation can data (SDA)This is a bidirectional pin used to transfer addressesand data into and out of the device.