24LC16B 16K I2C Serial EEPROM Extended (M) …

1 2009 Microchip Technology 124LC16 BDevice Selection Table Features: Single Supply with Operation down to Low-Power CMOS Technology:- Active current 1 mA, typical- Standby current, 1 A, typical 2- wire Serial Interface, I2C compatible Schmitt Trigger inputs for Noise Suppression Output Slope Control to eliminate Ground Bounce 100 kHz and 400 kHz Clock Compatibility Page Write Time 5 ms Max. Self-Timed Erase/Write Cycle 16-Byte Page Write Buffer Hardware Write-Protect ESD Protection > 4,000V More than 1 Million Erase/Write Cycles Data Retention > 200 Years Factory Programming Available Pb-Free and RoHS Compliant Temperature Ranges: - Extended (M): -55 C to +125 CDescription:The Microchip Technology Inc.

2 24LC16B is a 16 Kbit Electrically Erasable PROM. The device is organized as eight blocks of 256 x 8-bit memory with a 2- wire Serial interface. Low-voltage design permits operation down to with standby and active currents of only 1 A and 1 mA, respectively. The 24LC16B also has a page write capability for up to 16 bytes of data. The 24LC16B is available in the standard 8-pin SOIC Types Block Diagram Part NumberVCC RangeMax. Clock FrequencyTemp. kHzMNote 1:100 kHz for VCC < :Pins A0, A1 and A2 are not used by the 24LC16B (no internal connections).

3 HV EEPROM ArrayPage YDECXDECS ense ControlLatchesGenerator16K I2C Serial EEPROM Extended (M) Operating Temperatures24LC16 BDS22213A-page 2 2009 Microchip Technology CHARACTERISTICSA bsolute Maximum Ratings ( ) inputs and outputs to VCC + temperature ..-65 C to +150 CAmbient temperature with power applied ..-55 C to +125 CESD protection on all 4 kVTABLE 1-1:DC CHARACTERISTICS NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied.

4 Exposure to maximum rating conditions for Extended periods may affect device CHARACTERISTICSE xtended (M): TA = -55 C to +125 C, VCC = + to + , SCL and SDA pins D2 High-level input VCC V D3 VILLow-level input voltage VCCV D4 VHYSH ysteresis of Schmitt Trigger VCC V(Note 1)D5 VOLLow-level output voltage = mA, VCC = leakage current 1 AVIN = VSS or VCCD7 ILOO utput leakage current 1 AVOUT = VSS or VCCD8 CIN, COUTPin capacitance (all inputs/outputs) 10pFVCC = (Note 1)TA = 25 C, FCLK = 1 MHzD9 ICC writeOperating current 3mAVCC = , SCL = 400 kHzD10 ICC read D11 ICCSS tandby current 15 A A85 C125 CSDA = SCL = VCCWP = VSSNote 1.

5 This parameter is periodically sampled and not 100% :Typical measurements taken at room temperature. 2009 Microchip Technology 324LC16 BTABLE 1-2:AC CHARACTERISTICS AC CHARACTERISTICSE xtended (M): TA = -55 C to +125 C, VCC = + to + frequency 400kHz2 THIGHC lock high time600 ns3 TLOWC lock low time1300 ns4 TRSDA and SCL rise time (Note 1) 300ns(Note 1)5 TFSDA and SCL fall time 300ns(Note 1)6 THD:STAS tart condition hold time6004000 ns7 TSU:STAS tart condition setup time600 ns8 THD:DATData input hold time0 ns(Note 2)9 TSU:DATData input setup time100 ns10 TSU:STOStop condition setup time600 ns11 TAAO utput valid from clock (Note 2) 900ns12 TBUFBus free time.

6 Time the bus must be free before a new transmission can start1300 ns13 TOFO utput fall time from VIH minimum to VIL maximum20+ filter spike suppression (SDA and SCL pins) 50ns(Notes 1 and 3)15 TWCW rite cycle time (byte or page) 5ms16 Endurance1M cycles 25 C, (Note 4)Note 1:Not 100% tested. CB = total capacitance of one bus line in :As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop :The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression.

7 This eliminates the need for a TI specification for standard :This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained from Microchip s web site at 4 2009 Microchip Technology 1-1:BUS TIMING DATAFIGURE 1-2:BUS TIMING START/STOP 752489101211146 SCLSDAINSDAOUT376D410 StartStopSCLSDA 2009 Microchip Technology DESCRIPTIONSThe descriptions of the pins are listed in Table 2-1:PIN FUNCTION TABLE Address/Data Input/Output (SDA)SDA is a bidirectional pin used to transfer addresses and data into and out of the device.

8 Since it is an open-drain terminal, the SDA bus requires a pull-up resistor to VCC (typical 10 k for 100 kHz, 2 k for 400 kHz).For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating Start and Stop Clock (SCL)The SCL input is used to synchronize the data transferto and from the (WP) The WP pin must be connected to either VSS or tied to VSS, normal memory operation is enabled (read/write the entire memory 000-7FF).If tied to VCC, write operations are inhibited. The entire memory will be write-protected.

9 Read operations are not , A1, A2 The A0, A1 and A2 pins are not used by the 24LC16B . They may be left floating or tied to either VSS or ConnectedA12 Not ConnectedA23 Not ConnectedVSS4 GroundSDA5 Serial Address/Data I/OSCL6 Serial ClockWP7 Write-Protect InputVCC8+ to Power Supply24LC16 BDS22213A-page 6 2009 Microchip Technology DESCRIPTIONThe 24LC16B supports a bidirectional, 2- wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter, while a device receiving data is defined as a receiver. The bus has to be controlled by a master device which generates the Serial Clock (SCL), controls the bus access and generates the Start and Stop conditions, while the 24LC16B works as slave.

10 Both master and slave can operate as transmitter or receiver, but the master device determines which mode is CHARACTERISTICSThe following bus protocol has been defined: Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop , the following bus conditions have been defined (Figure 4-1). Not Busy (A)Both data and clock lines remain Data Transfer (B)A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition.