27C256

1 27C256 . 256K (32K x 8) CMOS EPROM. FEATURES PACKAGE TYPES. TSOP. High speed performance OE 1 28 A10. - 90 ns access time available A11 2 27 CE. CMOS Technology for low power consumption A9 3 26 D7. A8 4 25 D6. - 20 mA Active current A13 5 24 D5. A14 6 23. - 100 A Standby current D4. 27C256 . VCC 7 22 D3. Factory programming available VPP 21. 8 VSS. Auto-insertion-compatible plastic packages A12 9 20 D2. A7 10 19 D1. Auto ID aids automated programming A6 11 18 D0. A5 12 17 A0. Separate chip enable and output enable controls A4 13 16 A1. High speed express programming algorithm A3 14 15 A2. Organized 32K x 8: JEDEC standard pinouts PLCC. A12. A14. A13. Vcc VPP. NU. A7. - 28-pin Dual-in-line package 4. 3. 2. 1. 32. 31. 30. - 32-pin PLCC Package A6 5 29 A8. - 28-pin SOIC package A5 6 28 A9. A4 7 27 A11. - 28-pin Thin Small Outline Package (TSOP). 27C256 .

2 A3 8 26 NC. A2 9 OE. - 28-pin Very Small Outline Package (VSOP) 25. A1 10 24 A10. - Tape and reel A0 11 23 CE. NC 12 22 O7. Data Retention > 200 years O0 13 21 O6. Available for the following temperature ranges: 14. 15. 16. 17. 18. 19. 20. O1. O2. NU. O3. O4. O5. - Commercial: 0 C to +70 C VSS. DIP/SOIC. - Industrial: -40 C to +85 C. - Automotive: -40 C to +125 C. VPP 1 28 VCC. A12 2 27 A14. DESCRIPTION A7 3 26 A13. A6 4 25 A8. A5 5 24 A9. The Microchip Technology Inc. 27C256 is a CMOS A4 6 23 A11. 27C256 . 256K bit electrically Programmable Read Only Memory A3 7 22 OE. (EPROM). The device is organized as 32K words by 8 A2 8 21 A10. A1 9 20 CE. bits (32K bytes). Accessing individual bytes from an A0 10 19 O7. address transition or from power-up (chip enable pin O0 11 18 O6. O1. going low) is accomplished in less than 90 ns. This very 12 17 O5. O2 13 16 O4.

3 High speed device allows the most sophisticated micro- VSS 14 15 O3. processors to run at full speed without the need for WAIT states. CMOS design and processing enables VSOP. this part to be used in systems where reduced power consumption and reliability are requirements. OE 22 21 A10. A11 23 20 CE. A complete family of packages is offered to provide the A9 24 19 O7. most flexibility in applications. For surface mount appli- A8 25 18 O6. A13 26 17 O5. cations, PLCC, SOIC, VSOP or TSOP packaging is 27C256 . A14 27 16 O4. available. Tape and reel packaging is also available for VCC 28 15 O3. VPP 1 14 VSS. PLCC or SOIC packages. A12 2 13 O2. A7 3 12 O1. A6 4 11 O0. A5 5 10 A0. A4 6 9 A1. A3 7 8 A2. 1996 Microchip Technology Inc. DS11001L-page 1. This document was created with FrameMaker 4 0 4. 27C256 . ELECTRICAL CHARACTERISTICS TABLE 1-1: PIN FUNCTION TABLE.

4 Maximum Ratings* Name Function VCC and input voltages VSS .. to + A0-A14 Address Inputs VPP voltage VSS during CE Chip Enable programming .. to + OE Output Enable Voltage on A9 VSS .. to + Output voltage VSS .. to VCC + VPP Programming Voltage Storage temperature .. -65 C to +150 C O0 - O7 Data Output Ambient temp. with power applied .. -65 C to +125 C VCC +5V Power Supply *Notice: Stresses above those listed under Maximum Ratings VSS Ground may cause permanent damage to the device. This is a stress rat- ing only and functional operation of the device at those or any NC No Connection; No Internal Connec- other conditions above those indicated in the operation listings of tion this specification is not implied. Exposure to maximum rating con- ditions for extended periods may affect device reliability. NU Not Used; No External Connection Is Allowed TABLE 1-2: READ OPERATION DC CHARACTERISTICS.

5 VCC = +5V ( 10%). Commercial: Tamb = 0 C to +70 C. Industrial: Tamb = -40 C to +85 C. Extended (Automotive): Tamb = -40 C to +125 C. Parameter Part* Status Symbol Min. Max. Units Conditions Input Voltages all Logic "1" VIH VCC+1 V. Logic "0" VIL V. Input Leakage all ILI -10 10 A VIN = 0 to VCC. Output Voltages all Logic "1" VOH V IOH = -400 A. Logic "0" VOL V IOL = mA. Output Leakage all ILO -10 10 A VOUT = 0V to VCC. Input Capacitance all CIN 6 pF VIN = 0V; Tamb = 25 C;. f = 1 MHz Output Capacitance all COUT 12 pF VOUT = 0V; Tamb = 25 C;. f = 1 MHz Power Supply Current, C TTL input ICC1 20 mA VCC = ; VPP = VCC. Active I,E TTL input ICC2 25 mA f = 1 MHz;. OE = CE = VIL;. IOUT = 0 mA;. VIL = to ;. VIH = to VCC;. Note 1. Power Supply Current, C TTL input ICC(S) 2 mA. Standby I, E TTL input 3 mA. all CMOS input 100 A CE = VCC IPP Read Current all Read Mode IPP 100 A VPP = VPP Read Voltage all Read Mode VPP VCC V.

6 * Parts: C=Commercial Temperature Range; I, E=Industrial and Extended Temperature Ranges Note 1: Typical active current increases .75 mA per MHz up to operating frequency for all temperature ranges. DS11001L-page 2 1996 Microchip Technology Inc. 27C256 . TABLE 1-3: READ OPERATION AC CHARACTERISTICS. AC Testing Waveform: VIH = and VIL = ; VOH = VOL = Output Load: 1 TTL Load + 100 pF. Input Rise and Fall Times: 10 ns Ambient Temperature: Commercial: Tamb = 0 C to +70 C. Industrial: Tamb = -40 C to +85 C. Automotive: Tamb = -40 C to +125 C. 27C256 -90* 27C256 -10* 27C256 -12 27C256 -15 27C256 -20. Parameter Sym Units Conditions Min Max Min Max Min Max Min Max Min Max Address to Output tACC 90 100 120 150 200 ns CE=OE =VIL. Delay CE to Output Delay tCE 90 100 120 150 200 ns OE = VIL. OE to Output Delay tOE 40 45 55 65 75 ns CE = VIL. CE or OE to O/P tOFF 0 30 0 30 0 35 0 50 0 55 ns High Impedance Output Hold from tOH 0 0 0 0 0 ns Address CE or OE, whichever goes first * -10, -90 AC Testing Waveform: VIH = and VIL =.

7 45V; VOH = and VOL = Output Load: 1 TTL Load + 30pF. FIGURE 1-1: READ WAVEFORMS. VIH. Address Address Valid VIL. VIH. CE. VIL. t CE(2). VIH. OE. VIL t OFF(1,3). t OE(2). t OH. VOH. Outputs High Z High Z. O0 - O7 Valid Output VOL. t ACC. Notes: (1) tOFF is specified for OE or CE, whichever occurs first (2) OE may be delayed up to t CE - t OE after the falling edge of CE without impact on tCE. (3) This parameter is sampled and is not 100% tested. 1996 Microchip Technology Inc. DS11001L-page 3. 27C256 . TABLE 1-4: PROGRAMMING DC CHARACTERISTICS. Ambient Temperature: Tamb = 25 C 5 C. VCC = , VPP = VH = Parameter Status Symbol Min Max. Units Conditions Input Voltages Logic 1 VIH VCC+1 V. Logic 0 VIL V. Input Leakage ILI -10 10 A VIN = 0V to VCC. Output Voltages Logic 1 VOH V IOH = -400 A. Logic 0 VOL V IOL = mA. VCC Current, program & verify ICC2 20 mA Note 1.

8 VPP Current, program IPP2 25 mA Note 1. A9 Product Identification VH V. Note 1: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. TABLE 1-5: PROGRAMMING AC CHARACTERISTICS. for Program, Program Verify AC Testing Waveform: VIH= and VIL= ; VOH= ; VOL= and Program Inhibit Modes Output Load: 1 TTL Load + 100pF. Ambient Temperature: Tamb=25 C 5 C. VCC= , VPP = VH = Parameter Symbol Min. Max. Units Remarks Address Set-Up Time tAS 2 s Data Set-Up Time tDS 2 s Data Hold Time tDH 2 s Address Hold Time tAH 0 s Float Delay (2) tDF 0 130 ns VCC Set-Up Time tVCS 2 s Program Pulse Width (1) tPW 95 105 s 100 s typical CE Set-Up Time tCES 2 s OE Set-Up Time tOES 2 s VPP Set-Up Time tVPS 2 s Data Valid from OE tOE 100 ns Note 1: For express algorithm, initial programming width tolerance is 100 s 5%. 2: This parameter is only sampled and not 100% tested.

9 Output float is defined as the point where data is no longer driven (see timing diagram). DS11001L-page 4 1996 Microchip Technology Inc. 27C256 . FIGURE 1-2: PROGRAMMING WAVEFORMS. Program Verify VIH. Address Address Stable VIL. t AS. VIH t AH. High Z. Data Data Stable Data Out Valid VIL. t DS t DH t DF. (1). (2). VPP. tVPS. (2). VCC. tVCS. VIH. CE. VIL. t PW t OES. VIH t OE. OE (1). VIL. Notes: (1) t DF and tOE are characteristics of the device but must be accommodated by the programmer (2) VCC = V , VPP = V H = for express algorithm TABLE 1-6: MODES. Operation Mode CE OE VPP A9 O0 - O7. Read VIL VIL VCC X DOUT. Program VIL VIH VH X DIN. Program Verify VIH VIL VH X DOUT. Program Inhibit VIH VIH VH X High Z. Standby VIH X VCC X High Z. Output Disable VIL VIH VCC X High Z. Identity VIL VIL VCC VH Identity Code X = Don't Care Read Mode For Read operations, if the addresses are stable, the address access time (tACC) is equal to the delay from (See Timing Diagrams and AC Characteristics) CE to output (tCE).

10 Data is transferred to the output Read Mode is accessed when: after a delay from the falling edge of OE (tOE). a) the CE pin is low to power up (enable) the chip b) the OE pin is low to gate the data to the output pins 1996 Microchip Technology Inc. DS11001L-page 5. 27C256 . Standby Mode Verify The standby mode is defined when the CE pin is high After the array has been programmed it must be veri- (VIH) and a program mode is not defined. fied to ensure all the bits have been correctly pro- When these conditions are met, the supply current will grammed. This mode is entered when all the following drop from 20 mA to 100 A. conditions are met: a) VCC is at the proper level, Output Enable b) VPP is at the proper VH level, This feature eliminates bus contention in multiple bus c) the CE line is high, and microprocessor systems and the outputs go to a high d) the OE line is low.