512Bytes EEPROM 8-bit Atmel with 8KBytes In- System ...

1 Features High-performance, Low-power Atmel AVR 8-bit Microcontroller Advanced RISC Architecture 130 Powerful Instructions Most Single-clock Cycle Execution 32 8 General Purpose Working Registers Fully Static Operation Up to 16 MIPS Throughput at 16 MHz On-chip 2-cycle Multiplier High Endurance Non-volatile Memory segments 8 Kbytes of In- System Self-programmable Flash program memory 512 Bytes EEPROM 1 Kbyte Internal SRAM Write/Erase Cycles: 10,000 Flash/100,000 EEPROM Data retention: 20 years at 85 C/100 years at 25 C(1) Optional Boot Code Section with Independent Lock BitsIn- System Programming by On-chip Boot ProgramTrue Read-While-Write Operation Programming Lock for Software Security Peripheral Features Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode Real Time Counter with Separate Oscillator Three PWM Channels 8-channel ADC in TQFP and QFN/MLF packageEight Channels 10-bit Accuracy 6-channel ADC in PDIP packageSix Channels 10-bit Accuracy Byte-oriented Two-wire Serial Interface Programmable Serial USART Master/Slave SPI Serial Interface Programmable Watchdog Timer with Separate On-chip Oscillator On-chip Analog Comparator Special Microcontroller Features Power-on Reset and Programmable Brown-out Detection Internal Calibrated RC Oscillator External and Internal Interrupt Sources Five Sleep Modes.

2 Idle, ADC Noise Reduction, Power-save, Power-down, and Standby I/O and Packages 23 Programmable I/O Lines 28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLF Operating Voltages - (ATmega8L) - (ATmega8) Speed Grades 0 - 8 MHz (ATmega8L) 0 - 16 MHz (ATmega8) Power Consumption at 4 Mhz, 3V, 25 C Active: Idle Mode: Power-down Mode: A8-bit Atmel with 8 KBytes In-SystemProgrammable FlashAT m e g a AVR 02/201322486AA AVR 02/2013 ATmega8(L)Pin Configurations123456782423222120191817(I NT1) PD3(XCK/T0) PD4 GNDVCCGNDVCC(XTAL1/TOSC1) PB6(XTAL2/TOSC2) PB7PC1 (ADC1)PC0 (ADC0)ADC7 GNDAREFADC6 AVCCPB5 (SCK)3231302928272625910111213141516(T1) PD5(AIN0) PD6(AIN1) PD7(ICP1) PB0(OC1A) PB1(SS/OC1B) PB2(MOSI/OC2) PB3(MISO) PB4PD2 (INT0)PD1 (TXD)PD0 (RXD)PC6 (RESET)PC5 (ADC5/SCL)PC4 (ADC4/SDA)PC3 (ADC3)PC2 (ADC2)TQFP Top View123456789101112131428272625242322212 01918171615(RESET) PC6(RXD) PD0(TXD) PD1(INT0) PD2(INT1) PD3(XCK/T0) PD4 VCCGND(XTAL1/TOSC1) PB6(XTAL2/TOSC2) PB7(T1) PD5(AIN0) PD6(AIN1) PD7(ICP1) PB0PC5 (ADC5/SCL)PC4 (ADC4/SDA)PC3 (ADC3)PC2 (ADC2)PC1 (ADC1)PC0 (ADC0)GNDAREFAVCCPB5 (SCK)PB4 (MISO)PB3 (MOSI/OC2)PB2 (SS/OC1B)PB1 (OC1A)PDIP123456782423222120191817323130 2928272625910111213141516 MLF Top View(INT1) PD3(XCK/T0) PD4 GNDVCCGNDVCC(XTAL1/TOSC1) PB6(XTAL2/TOSC2) PB7PC1 (ADC1)

3 PC0 (ADC0)ADC7 GNDAREFADC6 AVCCPB5 (SCK)(T1) PD5(AIN0) PD6(AIN1) PD7(ICP1) PB0(OC1A) PB1(SS/OC1B) PB2(MOSI/OC2) PB3(MISO) PB4PD2 (INT0)PD1 (TXD)PD0 (RXD)PC6 (RESET)PC5 (ADC5/SCL)PC4 (ADC4/SDA)PC3 (ADC3)PC2 (ADC2)NOTE:The large center pad underneath the MLF packages is made of metal and internally connected to GND. It should be soldered or glued to the PCB to ensure good mechanical stability. If the center pad is left unconneted, the package might loosen from the AVR 02/2013 ATmega8(L)OverviewThe Atmel AVR ATmega8 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8 achievesthroughputs approaching 1 MIPS per MHz, allowing the System designer to optimize power con-sumption versus processing DiagramFigure 1. Block DiagramINTERNALOSCILLATOROSCILLATORWATCH DOGTIMERMCU DRIVERS/BUFFERSPORTC DIGITAL INTERFACEGENERALPURPOSEREGISTERSXYZALU+- PORTB DRIVERS/BUFFERSPORTB DIGITAL INTERFACEPORTD DIGITAL INTERFACEPORTD DRIVERS/BUFFERSXTAL1 XTAL2 CONTROLLINESVCCGNDMUX &ADCAGNDAREFPC0 - PC6PB0 - PB7PD0 - PD7 AVR CPUTWIRESET42486AA AVR 02/2013 ATmega8(L)The Atmel AVR core combines a rich instruction set with 32 general purpose working the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two inde-pendent registers to be accessed in one single instruction executed in one clock cycle.

4 Theresulting architecture is more code efficient while achieving throughputs up to ten times fasterthan conventional CISC ATmega8 provides the following features: 8 Kbytes of In- System Programmable Flash withRead-While-Write capabilities, 512 bytes of EEPROM , 1 Kbyte of SRAM, 23 general purposeI/O lines, 32 general purpose working registers, three flexible Timer/Counters with comparemodes, internal and external interrupts, a serial programmable USART, a byte oriented Two-wire Serial Interface, a 6-channel ADC (eight channels in TQFP and QFN/MLF packages) with10-bit accuracy, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port,and five software selectable power saving modes. The Idle mode stops the CPU while allowingthe SRAM, Timer/Counters, SPI port, and interrupt System to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip func-tions until the next Interrupt or Hardware Reset.

5 In Power-save mode, the asynchronous timercontinues to run, allowing the user to maintain a timer base while the rest of the device is sleep-ing. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronoustimer and ADC, to minimize switching noise during ADC conversions. In Standby mode, thecrystal/resonator Oscillator is running while the rest of the device is sleeping. This allows veryfast start-up combined with low-power device is manufactured using Atmel s high density non-volatile memory technology. TheFlash Program memory can be reprogrammed In- System through an SPI serial interface, by aconventional non-volatile memory programmer, or by an On-chip boot program running on theAVR core. The boot program can use any interface to download the application program in theApplication Flash memory. Software in the Boot Flash Section will continue to run while theApplication Flash Section is updated, providing true Read-While-Write operation.

6 By combiningan 8-bit RISC CPU with In- System Self-Programmable Flash on a monolithic chip, the AtmelATmega8 is a powerful microcontroller that provides a highly-flexible and cost-effective solutionto many embedded control ATmega8 is supported with a full suite of program and System development tools, includingC compilers, macro assemblers, program simulators, and evaluation values contained in this datasheet are based on simulations and characterization ofother AVR microcontrollers manufactured on the same process technology. Minimum and Maxi-mum values will be available after the device is AVR 02/2013 ATmega8(L)Pin DescriptionsVCCD igital supply B ( ) XTAL1/XTAL2/TOSC1/TOSC2 Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). ThePort B output buffers have symmetrical drive characteristics with both high sink and sourcecapability. As inputs, Port B pins that are externally pulled low will source current if the pull-upresistors are activated.

7 The Port B pins are tri-stated when a reset condition becomes active,even if the clock is not on the clock selection fuse settings, PB6 can be used as input to the inverting Oscil-lator amplifier and input to the internal clock operating on the clock selection fuse settings, PB7 can be used as output from the invertingOscillator the Internal Calibrated RC Oscillator is used as chip clock source, is used as for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is various special features of Port B are elaborated in Alternate Functions of Port B on page58 and System Clock and Clock Options on page C ( )Port C is an 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). ThePort C output buffers have symmetrical drive characteristics with both high sink and sourcecapability. As inputs, Port C pins that are externally pulled low will source current if the pull-upresistors are activated. The Port C pins are tri-stated when a reset condition becomes active,even if the clock is not the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin.

8 Note that the electrical char-acteristics of PC6 differ from those of the other pins of Port the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pinfor longer than the minimum pulse length will generate a Reset, even if the clock is not minimum pulse length is given in Table 15 on page 38. Shorter pulses are not guaranteed togenerate a various special features of Port C are elaborated on page D ( )Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). ThePort D output buffers have symmetrical drive characteristics with both high sink and sourcecapability. As inputs, Port D pins that are externally pulled low will source current if the pull-upresistors are activated. The Port D pins are tri-stated when a reset condition becomes active,even if the clock is not D also serves the functions of various special features of the ATmega8 as listed on input. A low level on this pin for longer than the minimum pulse length will generate areset, even if the clock is not running.

9 The minimum pulse length is given in Table 15 on page38. Shorter pulses are not guaranteed to generate a AVR 02/2013 ATmega8(L)AVCCAVCC is the supply voltage pin for the A/D Converter, Port C ( ), and ADC ( ). It should beexternally connected to VCC, even if the ADC is not used. If the ADC is used, it should be con-nected to VCC through a low-pass filter. Note that Port C ( ) use digital supply voltage, is the analog reference pin for the A/D (TQFP and QFN/MLF Package Only)In the TQFP and QFN/MLF package, serve as analog inputs to the A/D pins are powered from the analog supply and serve as 10-bit ADC AVR 02/2013 ATmega8(L)ResourcesA comprehensive set of development tools, application notes and datasheets are available fordownload on RetentionReliability Qualification results show that the projected data retention failure rate is much lessthan 1 PPM over 20 years at 85 C or 100 years at 25 AVR 02/2013 ATmega8(L)About Code ExamplesThis datasheet contains simple code examples that briefly show how to use various parts of thedevice.

10 These code examples assume that the part specific header file is included before compi-lation. Be aware that not all C compiler vendors include bit definitions in the header files andinterrupt handling in C is compiler dependent. Please confirm with the C compiler documentationfor more AVR 02/2013 ATmega8(L) Atmel AVR CPU CoreIntroductionThis section discusses the Atmel AVR core architecture in general. The main function of theCPU core is to ensure correct program execution. The CPU must therefore be able to accessmemories, perform calculations, control peripherals, and handle OverviewFigure 2. Block Diagram of the AVR MCU Architecture In order to maximize performance and parallelism, the AVR uses a Harvard architecture withseparate memories and buses for program and data. Instructions in the Program memory areexecuted with a single level pipelining. While one instruction is being executed, the next instruc-tion is pre-fetched from the Program memory.