64-Pin, Low-Power, High-Performance Microcontrollers with ...

1 PIC18(L)F67K40 64-Pin, Low-Power, High-Performance Microcontrollerswith XLP TechnologyDescriptionThese PIC18(L)F67K40 Microcontrollers feature Analog, Core Independent Peripherals andCommunication Peripherals, combined with eXtreme Low-Power (XLP) technology for a wide range ofgeneral purpose and low-power applications. These 64-pin devices are equipped with a 10-bit ADC withComputation (ADCC) automating Capacitive Voltage Divider (CVD) techniques for advanced touchsensing, averaging, filtering, oversampling and performing automatic threshold comparisons. They alsooffer a set of Core Independent Peripherals such as Complementary Waveform Generator (CWG),Windowed Watchdog Timer (WWDT), Cyclic Redundancy Check (CRC)/Memory Scan, Zero-CrossDetect (ZCD) and Peripheral Pin Select (PPS), providing for increased design flexibility and lower Features C Compiler Optimized RISC Architecture Operating Speed.

2 DC 64 MHz clock input over the full VDD range ns minimum instruction cycle Programmable 2-Level Interrupt Priority 31-Level Deep Hardware Stack Four 8-Bit Timers (TMR2/4/6/7) with Hardware Limit Timer (HLT) Five 16-Bit Timers (TMR0/1/3/5/7) Low-Current Power-on Reset (POR) Power-up Timer (PWRT) Brown-out Reset (BOR) Low-Power BOR (LPBOR) Option Windowed Watchdog Timer (WWDT): Watchdog Reset on too long or too short interval between watchdog clear events Variable prescaler selection Variable window size selection All sources configurable in hardware or softwareMemory 128k bytes Program flash Memory 3562 Bytes Data SRAM Memory 2017 Microchip Technology Inc.

3 DatasheetDS40001841D-page 1 1024 Bytes Data EEPROM Programmable Code Protection Direct, Indirect and Relative Addressing modesOperating Characteristics Operating Voltage Ranges: to (PIC18LF67K40 ) to ( PIC18F67K40) Temperature Range: Industrial: -40 C to 85 C Extended: -40 C to 125 CPower-Saving Operation Modes Doze: CPU and Peripherals Running at Different Cycle Rates (typically CPU is lower) Idle: CPU Halted While Peripherals Operate Sleep: Lowest Power Consumption Peripheral Module Disable (PMD): Ability to selectively disable hardware module to minimize active power consumption of unusedperipherals Extreme Low-Power mode (XLP) Sleep: 500 nA typical @ Sleep and Watchdog Timer: 900 nA typical @ Low-Power (XLP) Features Sleep mode: 50 nA @ , typical Windowed Watchdog Timer: 500 nA @ , typical Secondary Oscillator: 500 nA @ 32 kHz Operating Current: 8 uA @ 32 kHz, , typical 32 uA/MHz @ , typicalDigital Peripherals Complementary Waveform Generator (CWG).

4 Rising and falling edge dead-band control Full-bridge, half-bridge, 1-channel drive Multiple signal sources Capture/Compare/PWM (CCP) modules: Five CCPs 16-bit resolution for Capture/Compare modes 10-bit resolution for PWM mode 10-Bit Pulse-Width Modulators (PWM): PIC18(L)F67K40 2017 Microchip Technology Inc. DatasheetDS40001841D-page 2 Two 10-bit PWMs Serial Communications: Five Enhanced USART (EUSART) with Auto-Baud Detect, Auto-wake-up on Start. RS-232, RS-485, LIN compatible SPI I2C, SMBus and PMBus compatible Up to 59 I/O Pins and One Input Pin: Individually programmable pull-ups Slew rate control Interrupt-on-change Input level selection control Programmable CRC with Memory Scan: Reliable data/program memory monitoring for Fail-Safe operation ( , Class B) Calculate CRC over any portion of flash or EEPROM High-speed or background operation Hardware Limit Timer (TMR2/4/6/8+HLT): Hardware monitoring and Fault detection Peripheral Pin Select (PPS).

5 Enables pin mapping of digital I/O Data Signal Modulator (DSM) Two Signal Measurement Timer (SMT1/2): 24-bit timer/counter with prescaler Multiple gate and clock inputsAnalog Peripherals 10-Bit Analog-to-Digital Converter with Computation (ADC2): 47 external channels Conversion available during Sleep Four internal analog channels Internal and external trigger options Automated math functions on input signals: Averaging, filter calculations, oversampling and threshold comparison 8-bit hardware acquisition timer Hardware Capacitive Voltage Divider (CVD) Support: 8-bit precharge timer Adjustable sample and hold capacitor array Guard ring digital output drive Zero-Cross Detect (ZCD): Detect when AC signal on pin crosses ground 5-Bit Digital-to-Analog Converter (DAC): Output available externally Programmable 5-bit voltage (% of VDD,[VRef+ - VRef-], FVR) Internal connections to Comparators and ADC PIC18(L)F67K40 2017 Microchip Technology Inc.

6 DatasheetDS40001841D-page 3 Three Comparators (CMP): Five external inputs External output via PPS Fixed Voltage Reference (FVR) module: , and output levels Two buffered outputs: One for DAC/CMP and one for ADCC locking Structure High-Precision Internal Oscillator Block (HFINTOSC): Selectable frequencies up to 64 MHz 1% at calibration 32 kHz Low-Power Internal Oscillator (LFINTOSC) External 32 kHz Crystal Oscillator (SOSC) External High-frequency Oscillator Block: Three crystal/resonator modes Digital Clock Input mode 4x PLL with external sources Fail-Safe Clock Monitor: Allows for safe shutdown if external clock stops Oscillator Start-up Timer (OST)Programming/Debug Features In-Circuit Serial Programming (ICSP ) via Two Pins In-Circuit Debug (ICD) with Three Breakpoints via Two Pins Debug Integrated On-ChipPIC18(L)F67K40 Family TypesTable 1.

7 Devices included in this data sheetDeviceProgram Memory flash (bytes)Data SRAM(bytes)Data EEPROM(bytes)I/O Pins16-bit TimersComparators10-bit ADC2 withComputation (ch)5-bit DACZero-Cross DetectCCP/10-bit PWMCWGSMTLow Voltage Detect (LVD)8-bit TMR with HLTW indowed WatchdogTimerCRC with Memory ScanEUSARTI2C/SPIPPSP eripheral Module DisableTemperature IndicatorDebug(1)PIC18(L)F67K40128k35681 024605347115/21214YY52 YYYI PIC18(L)F67K40 2017 Microchip Technology Inc. DatasheetDS40001841D-page 4 Table 2. Devices not included in this data sheetDeviceProgram Memory flash (bytes)Data SRAM(bytes)Data EEPROM(bytes)I/O Pins16-bit TimersComparators10-bit ADC2 withComputation (ch)5-bit DACZero-Cross DetectCCP/10-bit PWMCWGSMTLow Voltage Detect (LVD)8-bit TMR with HLTW indowed WatchdogTimerCRC with Memory ScanEUSARTI2C/SPIPPSP eripheral Module DisableTemperature IndicatorDebug(1)PIC18(L)F24K4016k102425 6254224112/21013YY11 YYYIPIC18(L)F25K4032k2048256254224112/21 013YY11 YYYIPIC18(L)F26K4064k36151024254224112/2 1013YY22 YYYIPIC18(L)F27K40128k36151024254224112/ 21013YY22 YYYIPIC18(L)F45K4032k2048256364235112/21 013YY22 YYYIPIC18(L)

8 F46K4064k36151024364235112/21013YY22 YYYIPIC18(L)F47K40128k36151024364235112/ 21013YY22 YYYIPIC18(L)F65K4032k20481024605345115/2 1214YY52 YYYIPIC18(L)F66K4064k35621024605345115/2 1214YY52 YYYINote: Debugging Methods: (I) Integrated on Sheet Index:1. DS40001843 PIC18(L)F24/25K40 Data Sheet, 28-Pin, 8-bit flash Microcontrollers2. DS40001816 PIC18(L)F26/45/46K40 Data Sheet, 28/40/44-Pin, 8-bit flash Microcontrollers3. DS40001844 PIC18(L)F27/47K40 Data Sheet, 28/40/44-Pin, 8-bit flash Microcontrollers4. DS40001842 PIC18(L)F65/66K40 Data Sheet, 64-Pin, 8-bit flash Microcontrollers5. DS40001841 PIC18(L)F67K40 Data Sheet, 64-Pin, 8-bit flash Microcontrollers PIC18(L)F67K40 2017 Microchip Technology Inc.

9 DatasheetDS40001841D-page 5 Pin DiagramsFigure 1. 64-pin : 64-pin TQFPLast Edit:3/6/2017 First Used:N/ANotes:Generic 64-pin TQFP diagramRev. 00-000 064A3/6/201 76059RB0RB1 VSSRA6RA7 VDDRD1RH3RH2RE7RD0RB6RB2RB3RB5RE6RE5RE4R E3RE258575655544847461718192021222324252 627383940414243444510987654321RA5RH0RH1R A1RA0RA2RA3RG6RG7RF1RE1RE0 VPP/MCLR/RG5 VSSVDDRF7RG3RG0RG1RG21164636261RG4RF0RB4 RD2RD5RD4RD353525150RD615141312RF6RF4RF3 RF216RF549RD729303132RC7RC6RC0RC1RA428RC 5RC4RC3RC2RB73334353637 PIC18(L)F67K40 2017 Microchip Technology Inc. DatasheetDS40001841D-page 6 Figure 2. 64-pin : 64-pin QFNLast Edit:3/7/2017 First Used:N/ANotes:Generic 64-pin QFN diagram Rev.

10 00-000 064B3/7/201 760 59RB0RB1 VSSRA6RA7 VDDRD1RH3RH2RE7RD0RB6RB2RB3RB5RE6RE5RE4R E3RE258 57 56 55 5448474617 18 19 20 21 22 23 24 25 26 27383940414243444510987654321RA5RH0RH1RA 1RA0RA2RA3RG6RG7RF1RE1RE0 VPP/MCLR/RG5 VSSVDDRF7RG3RG0RG1RG21164 63 62 61RG4RF0RB4RD2RD5RD4RD353 52 51 50RD615141312RF6RF4RF3RF216RF549RD729 30 31 32RC7RC6RC0RC1RA428RC5RC4RC3RC2RB7333435 3637 Note: It is recommended that the exposed bottom pad be connected to VSS, however it must not be the onlyVSS connection to the Allocation TablesTable 1. 64-Pin Allocation TableI/O(2)64-PinTQFP,QFNA/DDACC omparatorTimersCCP andPWMCWGZCDSMTC lockReference(CLKR)InterruptEUSARTDSMMSS PB asicRA024 ANA0 C1IN4-C2IN4-C3IN4-T8IN(1) RA123 ANA1 T2IN(1) RA222 ANA2 Vref-Vref-C1IN1+C2IN1+C3IN1+ RA321 ANA3 Vref+Vref+ RA428 ANA4 T0 CKI(1) RA527 ANA5 T3G(1) RA640 ANA6 CLKOUTOSC2RA739 ANA7 OSC1 PIC18(L)F67K40 2017 Microchip Technology Inc.