8-bit Microcontroller with 1K Bytes In-System Programmable ...

1 Features High Performance, Low Power AVR 8-bit Microcontroller Advanced RISC Architecture 120 Powerful Instructions Most Single Clock Cycle Execution 32 x 8 General Purpose Working Registers Fully Static Operation Up to 20 MIPS Througput at 20 MHz High Endurance Non-volatile Memory segments 1K Bytes of In-System Self- Programmable Flash program memory 64 Bytes EEPROM 64 Bytes Internal SRAM Write/Erase Cycles: 10,000 Flash/100,000 EEPROM Data retention: 20 Years at 85 C/100 Years at 25 C (see page 6) Programming Lock for Self-Programming Flash & EEPROM Data Security Peripheral Features One 8-bit Timer/Counter with Prescaler and Two PWM Channels 4-channel, 10-bit ADC with Internal Volta ge Refe rence Programmable Watchdog Timer with Separate On-chip Oscillator On-chip Analog Comparator Special Microcontroller Features debugWIRE On-chip Debug System In-System Programmable via SPI Port External and Internal Interrupt Sources Low Power Idle, ADC Noise Reduction, and Power-down Modes Enhanced Power-on Reset Circuit Programmable Brown-out Detection Circuit with Software Disable Function Internal Calibrated Oscillator I/O and Packages 8-pin PDIP/SOIC.

2 Six Programmable I/O Lines 10-pad MLF: Six Programmable I/O Lines 20-pad MLF: Six Programmable I/O Lines Operating Voltage: Speed Grade: 0 4 MHz @ 0 10 MHz @ 0 20 MHz @ Industrial Temperature Range Low Power Consumption Active Mode: 190 A at V and 1 MHz Idle Mode: 24 A at V and 1 MHz8-bit Microcontroller with 1K Bytes In-SystemProgrammable FlashATtiny13 ARev. 8126F AVR 05/1228126F AVR 05/12 ATtiny13A1. Pin ConfigurationsFigure of ATtiny13A12348765(PCINT5/RESET/ADC0/dW) PB5(PCINT3/CLKI/ADC3) PB3(PCINT4/ADC2) PB4 GNDVCCPB2 (SCK/ADC1/T0/PCINT2)PB1 (MISO/AIN1/OC0B/INT0/PCINT1)PB0 (MOSI/AIN0/OC0A/PCINT0)8-PDIP/SOIC123452 0-QFN/MLF15141312112019181716678910(PCIN T5/RESET/ADC0/dW) PB5(PCINT3/CLKI/ADC3) PB3 DNCDNC(PCINT4/ADC2) PB4 DNCDNCGNDDNCDNCVCCPB2 (SCK/ADC1/T0/PCINT2)DNCPB1 (MISO/AIN1/OC0B/INT0/PCINT1)PB0 (MOSI/AIN0/OC0A/PCINT0)DNCDNCDNCDNCDNCNO TE: Bottom pad should be soldered to : Do Not Connect1234510-QFN/MLF10 9 8 7 6(PCINT5/RESET/ADC0/dW) PB5(PCINT3/CLKI/ADC3) PB3 DNC(PCINT4/ADC2) PB4 GNDVCCPB2 (SCK/ADC1/T0/PCINT2)DNCPB1 (MISO/AIN1/OC0B/INT0/PCINT1)PB0 (MOSI/AIN0/OC0A/PCINT0)NOTE.

3 Bottom pad should be soldered to : Do Not Connect38126F AVR 05 B (PB5:PB0)Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). ThePort B output buffers have symmetrical drive characteristics with both high sink and sourcecapability. As inputs, Port B pins that are externally pulled low will source current if the pull-upresistors are activated. The Port B pins are tri-stated when a reset condition becomes active,even if the clock is not B also serves the functions of various special features of the ATtiny13A as listed on input. A low level on this pin for longer than the minimum pulse length will generate areset, even if the clock is not running and provided the reset pin has not been disabled.

4 The min-imum pulse length is given in Table 18-4 on page 120. Shorter pulses are not guaranteed togenerate a reset pin can also be used as a (weak) I/O AVR 05/12 ATtiny13A2. OverviewThe ATtiny13A is a low-power CMOS 8-bit Microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny13A achievesthroughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con-sumption versus processing DiagramFigure DiagramPROGRAMCOUNTERINTERNALOSCILLATORW ATCHDOGTIMERSTACKPOINTERPROGRAMFLASHSRAM MCU CONTROLREGISTERGENERALPURPOSEREGISTERSIN STRUCTIONREGISTERTIMER/COUNTER0 INSTRUCTIONDECODERDATA BDATA REGISTERPORT BPROGRAMMINGLOGICTIMING ANDCONTROLMCU STATUSREGISTERSTATUSREGISTERALUPORT B DRIVERSPB[0.]

5 5]VCCGNDCONTROLLINES8-BIT DATABUSZ ADC / ANALOG COMPARATORINTERRUPTUNITCALIBRATEDYXRESET CLKIWATCHDOGOSCILLATORDATAEEPROM58126F AVR 05/12 ATtiny13 AThe AVR core combines a rich instruction set with 32 general purpose working registers. All 32registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independentregisters to be accessed in one single instruction executed in one clock cycle. The resultingarchitecture is more code efficient while achieving throughputs up to ten times faster than con-ventional CISC ATtiny13A provides the following features: 1K byte of In-System Programmable Flash, 64bytes EEPROM, 64 Bytes SRAM, 6 general purpose I/O lines, 32 general purpose working reg-isters, one 8-bit Timer/Counter with compare modes, Internal and External Interrupts, a 4-channel, 10-bit ADC, a Programmable Watchdog Timer with internal Oscillator, and three soft-ware selectable power saving modes.

6 The Idle mode stops the CPU while allowing the SRAM,Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. ThePower-down mode saves the register contents, disabling all chip functions until the next Inter-rupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modulesexcept ADC, to minimize switching noise during ADC device is manufactured using Atmel s high density non-volatile memory technology. TheOn-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPIserial interface, by a conventional non-volatile memory programmer or by an On-chip boot coderunning on the AVR ATtiny13A AVR is supported with a full suite of program and system development toolsincluding: C Compilers, Macro Assemblers, Program Debugger/Simulators, and Evaluation AVR 05/12 ATtiny13A3.

7 Comprehensive set of drivers, application notes, data sheets and descriptions on developmenttools are available for download at Examples This documentation contains simple code examples that briefly show how to use various parts ofthe device. These code examples assume that the part specific header file is included beforecompilation. Be aware that not all C compiler vendors include bit definitions in the header filesand interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-tation for more RetentionReliability Qualification results show that the projected data retention failure rate is much lessthan 1 PPM over 20 years at 85 C or 100 years at 25 AVR 05/12 ATtiny13A4.

8 CPU CoreThis section discusses the AVR core architecture in general. The main function of the CPU coreis to ensure correct program execution. The CPU must therefore be able to access memories,perform calculations, control peripherals, and handle OverviewFigure Diagram of the AVR Architecture In order to maximize performance and parallelism, the AVR uses a Harvard architecture withseparate memories and buses for program and data. Instructions in the Program memory areexecuted with a single level pipelining. While one instruction is being executed, the next instruc-tion is pre-fetched from the Program memory. This concept enables instructions to be executedin every clock cycle. The Program memory is In-System Reprogrammable Flash Lines32 x 8 GeneralPurposeRegistrersALUS tatusand ControlI/O LinesEEPROMData Bus 8-bit DataSRAMD irect AddressingIndirect AddressingInterruptUnitWatchdogTimerAnal ogComparatorI/O Module 2I/O Module1I/O Module n88126F AVR 05/12 ATtiny13 AThe fast-access Register File contains 32 x 8-bit general purpose working registers with a singleclock cycle access time.

9 This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-ical ALU operation, two operands are output from the Register File, the operation is executed,and the result is stored back in the Register File in one clock of the 32 registers can be used as three 16-bit indirect address register pointers for DataSpace addressing enabling efficient address calculations. One of the these address pointerscan also be used as an address pointer for look up tables in Flash Program memory. Theseadded function registers are the 16-bit X-, Y-, and Z-register, described later in this ALU supports arithmetic and logic operations between registers or between a constant anda register. Single register operations can also be executed in the ALU.

10 After an arithmetic opera-tion, the Status Register is updated to reflect information about the result of the flow is provided by conditional and unconditional jump and call instructions, able todirectly address the whole address space. Most AVR instructions have a single 16-bit word for-mat. Every Program memory address contains a 16- or 32-bit interrupts and subroutine calls, the return address Program Counter (PC) is stored on theStack. The Stack is effectively allocated in the general data SRAM, and consequently the Stacksize is only limited by the total SRAM size and the usage of the SRAM. All user programs mustinitialize the SP in the Reset routine (before subroutines or interrupts are executed). The StackPointer (SP) is read/write accessible in the I/O space.