AN2759: Implementing an Ethernet Interface with the …

1 Freescale Semiconductor, Inc., 2004. All rights reserved. Freescale SemiconductorApplication NoteThis product incorporates SuperFlash technology licensed from , 9/2004 Implementing an Ethernet Interface with the MC9S12NE64By: Bill Lucas and Steven Torres Systems Engineering Austin, TexasIntroductionThis application note provides recommendations for Implementing an Ethernet Interface with the MC9S12NE64 microcontroller unit (MCU). The discussion covers many topics including: Overview of the MC9S12NE64 including available packages Components required to add Ethernet functionality to the MC9S12NE64 MC9S12NE64 schematics showing the minimum system design Circuit connections between the MC9S12NE64 and a high-speed LAN magnetics isolation module and RJ45 connector General printed circuit board (PCB) layout recommendations for 10 and 100 Mbps Ethernet design High-speed LAN magnetics isolation module requirements Crystal placement and circuitry recommendations MC9S12NE64 Ethernet design examples in both 112-pin and 80-pin packagesImplementing an Ethernet Interface with the MC9S12NE64, Rev.

2 Freescale Semiconductor MC9S12NE64 Single-Chip Ethernet SolutionFigure 1 shows a preview of the design examples:Figure 1. Design ExamplesMC9S12NE64 Single-Chip Ethernet SolutionThis section introduces the MC9S12NE64 and provides an overview of the MC9S12NE64 integrated Ethernet controller and MC9S12NE64 system design. MC9S12NE64 OverviewThe MC9S12NE64 is a 16-bit MCU based on Freescale Semiconductor s HCS12 CPU platform. It includes 8K bytes of RAM and 64K bytes of FLASH memory. In the 80-pin package, the MC9S12NE64 has other standard on-chip peripherals including two asynchronous serial communications Interface modules (SCIs), one synchronous serial peripheral Interface (SPI), an inter-integrated circuit bus (IIC), a 4-channel/16-bit timer module (TIM), an 8-channel/10-bit analog-to-digital converter (ADC), and up to 18 pins available as keypad wake-up inputs (KWUs) or general-purpose I/O pins. In addition, an expanded bus that can be operated at 16 MHz1 is available on the 112-pin MC9S12NE64 introduces a new peripheral for the HCS12 CPU platform, an integrated Ethernet controller.

3 The MC9S12NE64 integrates an Ethernet controller that includes a media access controller (MAC) and a physical transceiver (PHY) in one die with the CPU, memory, and other HCS12 standard on-chip peripherals. The MC9S12NE64 integrated Ethernet controller is compatible with IEEE and specifications for 10-Mbps or 100-Mbps operation, At a 16-MHz internal bus speed, the MC9S12NE64 integrated Ethernet controller is limited to 10-Mbps operation. A 25-MHz internal bus speed is required for 100-Mbps Single-Chip Ethernet SolutionImplementing an Ethernet Interface with the MC9S12NE64, Rev. Semiconductor 3 The MC9S12NE64 can be targeted at low-throughput connectivity applications that require operation from a nominal power supply. With an on-chip bandgap-based voltage regulator (VREG), the internal digital supply voltage of V (VDD) will be generated internally. Figure 2 shows a block diagram of the MC9S12NE64.

4 More information on the MC9S12NE64 is available from the Freescale Semiconductor website: 2. Block Diagram of the MC9S12NE64MC9S12NE64 PackagesThe MC9S12NE64 is available in two packages. Table 1 provides device numbers for each package Figure 3 shows the 112-pin LQFP package pin-out. Figure 4 shows the 80-pin TQFP-EP package pin out. 112-pin LQFP package 70 I/O port pins and 10 input-only pins 80-pin TQFP-EP package 38 I/O port pins and 10 input-only pinsThe 80-pin TQFP-EP package does not have access to the multiplex address and data bus. It is designed for single-chip applications that use the internal FLASH and RAM memory. The 80-pin TQFP-EP package has an exposed flag for heat dissipation and requires special PCB layout to accommodate the flag. See the Exposed Flag l e 1. MC68 HCS908NE64 Package OptionsDevice NumberMask SetTempPackageMC9S12NE64 CFU0L19S 40 C, 85 C80 TQFP-EPMC9S12NE64 CPV0L19S 40 C, 85 C112 LQFPHCS12 CPU WITH DEBUG MODULE2 X SCISPIIICV REG VTO V CONVERTER18 KEY WAKEUPIRQ PORTSEPHYEMAC64K FLASH8K RAMATD10-BIT, 8 CHINTERNAL BUSTIMER 16-BIT, 4 CHImplementing an Ethernet Interface with the MC9S12NE64, Rev.

5 Freescale Semiconductor MC9S12NE64 Single-Chip Ethernet SolutionFigure 3. Pinout of MC9S12NE64 in 112-Pin LQFP PackagePL0/ACTLEDPL1/LNKLEDVDDRPL2/SPDLE DPA7/ADDR15/DATA15PA6/ADDR14/DATA14PA5/A DDR13/DATA13PA4/ADDR12/DATA12 PHY_VSSRXPHY_VDDRXPHY_RXN PHY_RXPPHY_VSSTXPHY_TXNPHY_TXPPHY_VDDTXP HY_VDDAPHY_VSSAPHY_RBIASVDD2 VSS2PA3/ADDR11/DATA11PA2/ADDR10/DATA10PA 1/ADDR9/DATA9PA0/ADDR8/DATA8PL3/DUPLEDPL 4/COLLEDBKGD/MODCPJ6/KWJ6/IIC_SDAPJ7/KWJ 7/IIC_SCLPT4/TIM_IOC4PT5/TIM_IOC5PT6/TIM _IOC6PT7/TIM_IOC7PK7/ECS/ROMCTLPK6/XCSPK 5/XADDR19PK4/XADDR18 VDD1 VSS1PK3/XADDR17PK2/XADDR16PK1/XADDR15PK0 /XADDR14 VSSAVRLVRHVDDAPAD7/AN7 PAD6/AN6 PAD5/AN5 PAD4/AN4 PAD3/AN3 PAD2/AN2 PAD1/AN1 PAD0/AN0 MII_TXER/KWH6/PH6 MII_TXEN/KWH5/PH5 MII_TXCLK/KWH4/PH4 MII_TXD3/KWH3/PH3 MII_TXD2/KWH2/PH2 MII_TXD1/KWH1/PH1 MII_TXD0/KWH0/PH0 MII_MDC/KWJ0/PJ0 MII_MDIO/KWJ1/PJ1 ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 VDDX1 VSSX1 ADDR4/DATA4/PB4 ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7

6 MII_CRS/KWJ2/PJ2 MII_COL/KWJ3/PJ3 MII_RXD0/KWG0/PG0 MII_RXD1/KWG1/PG1 MII_RXD2/KWG2/PG2 MII_RXD3/KWG3/PG3 MII_RXCLK/KWG4/PG4 MII_RXDV/KWG5/PG5 MII_RXER/KWG6/PG6 KWG7/PG7 SCI0_RXD/PS0 SCI0_TXD/PS1 SCI1_RXD/PS2 SCI1_TXD/PS3 SPI_MISO/PS4 SPI_MOSI/PS5 SPI_SCK/PS6 SPI_SS/PS7 NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSX2 VDDX2 RESETVDDPLLXFCVSSPLLEXTALXTALTESTPL6PL5 LSTRB/TAGLO/PE3R/W/PE2 IRQ/PE1 XIRQ/PE0 Signals shown in Bold are not available on the 80-pin Single-Chip Ethernet SolutionImplementing an Ethernet Interface with the MC9S12NE64, Rev. Semiconductor 5 Figure 4. Pinout of MC9S12NE64 in 80-Pin TQFP-EP PackageDesigning with the MC9S12NE64 and Adding an Ethernet InterfaceThe MC9S12NE64 is a single-chip Ethernet solution. Having built-in CPU, FLASH, RAM, MAC, and PHY reduces the cost of Implementing an embedded device with Ethernet connectivity, because no active external components are required.

7 The components required to enable the MC9S12NE64 Ethernet Interface include the following: MC9S12NE64 MCU 25-MHz crystal power supply External resistor for PHY_RBIAS pin (see data sheet for value of RBias) High-speed LAN magnetics isolation module RJ45 connector Miscellaneous capacitors and resistors Optional: PHY status LEDs (available in some integrated RJ45 connectors) Optional: Background debug (BDM) connector1234567891011121314151617181920 8079787776757473727170696867666564636261 2122232425262728293031323334353637383940 MC9S12NE64-Family80 TQFP-EPPL0/ACTLEDPL1/LNKLEDVDDRPL2/SPDLE DPHY_VSSRXPHY_VDDRXPHY_RXN PHY_RXPPHY_VSSTXPHY_TXNPHY_TXPPHY_VDDTXP HY_VDDAPHY_VSSAPHY_RBIASVDD2 VSS2PL3/DUPLEDPL4/COLLEDBKGD/MODCPJ6/KWJ 6/IIC_SDAPJ7/KWJ7/IIC_SCLPT4/TIM_IOC4/PT 5/TIM_IOC5PT6/TIM_IOC6PT7/TIM_IOC7 VDD1 VSS1 VSSAVRLVRHVDDAPA D 7 / A N 7PA D 6 / A N 6PA D 5 / A N 5PA D 4 / A N 4PA D 3 / A N 3PA D 2 / A N 2PA D 1 / A N 1PA D 0 / A N 0 MII_TXER/KWH6/PH6 MII_TXEN/KWH5/PH5 MII_TXCLK/KWH4/PH4 MII_TXD3/KWH3/PH3 MII_TXD2/KWH2/PH2 MII_TXD1/KWH1/PH1 MII_TXD0/KWH0/PH0 MII_MDC/KWJ0/PJ0 MII_MDIO/KWJ1/PJ1 VDDX1 VSSX1 MII_CRS/KWJ2/PJ2 MII_COL/KWJ3/PJ3 MII_RXD0/KWG0/PG0 MII_RXD1/KWG1/PG1 MII_RXD2/KWG2/PG2 MII_RXD3/KWG3/PG3 MII_RXCLK/KWG4/PG4 MII_RXDV/KWG5/PG5 MII_RXER/KWG6/PG6 SCI0_RXD/PS0 SCI0_TXD/PS1 SCI1_RXD/PS2 SCI1_TXD/PS3

8 SPI_MISO/PS4 SPI_MOSI/PS5 SPI_SCK/PS6 SPI_SS/PS7 ECLK/PE4 VSSX2 VDDX2 RESETVDDPLLXFCVSSPLLEXTALXTALTESTIRQ/PE1 XIRQ/PE060595857565554535251504948474645 44434241 Implementing an Ethernet Interface with the MC9S12NE64, Rev. Freescale Semiconductor MC9S12NE64 Single-Chip Ethernet SolutionFigure 5 is a schematic of a MC9S12NE64 minimum system circuit implementation using the MC9S12NE64 in an 80-pin package and the components described in this section. This circuit implementation shows an optional background debug connector (J1), and status LEDs (LED1 through LED5). The circuit also shows the required bias resistor (R5), high-speed LAN magnetics isolation module, and RJ45 Ethernet connector. Figure 5. MC9S12NE64 Minimum System Circuit Implementation in the 80-Pin PackageIn Figure 5, the MC9S12NE64 in the 80-pin package will operate in normal single-chip mode. Figure 5 shows that the design operates with the internal voltage regulator enabled.

9 Using the internal voltage regulator is the recommended configuration for the MC9S12NE64. Figure 5 also illustrates the basic MC9S12NE64 power and clock input requirements, which are described in following configure the MC9S12NE64 (in a 112-pin package) in normal single-chip mode, the MODC, MODB, and MODA pins may need to be pulled up or down. The operating mode of the MC9S12NE64, as well as other HCS12 MCUs, out of reset is determined by the states of MODC, MODB, and MODA during reset. MODC, MODB, and MODA can alternatively be configured by software. Table 2 describes the available modes on the 112-pin OHMS75 OHMS1000 pF2kVCABLE SIDEMCU SIDET1 TRANSFORMER / RJ-45 CONNECTORT+1CT2T-3R+ 3VJ1 BACKGROUND DEBUG113355224466* 1%PL1/LNKLEDPL3/DUPLEDPL2/SPDLED3. 3V3. 3V* .22PL0/ACTLEDPL4/ COLLEDLED3 DUP_L EDR7220 LED1 LNK_LEDR6220R8220 LED2 SPD_LEDY125 RXD/ PS021 SCI0_ TXD/ PS122 SCI1_ RXD/ PS223 SCI1_ TXD/ PS324 SPI_ MISO/ PS425 SPI_ MOSI/ PS526 SPI_ SCK/ PS627 SPI_SS/ PS728 VSSX230 VDDX231 RESET32 VDDPLL33 XFC34 VSSPLL35 EXTAL36 XTAL37 TEST38 IRQ/ PE139 XIRQ/ PE040 BKGD/MODC41PL4/COLLED42PL3/DUPLED43 VSS244 VDD245 PHY_RBIAS46 PHY_VSSA47 PHY_VDDA48 PHY_VDDTX49 PHY_TXP50 PHY_TXN51 PHY_VSSTX52 PHY_RXP53 PHY_RXN54 PHY_VDDRX55 PHY_VSSRX56PL2/SPDLED57 VDDR58PL1/LNKLED59PL0/ACTLED60 PAD0/ AN061 PAD1/ AN162 PAD2/ AN263 PAD3/ AN364 PAD4/ AN465 PAD5/ AN566 PAD6/ AN667 PAD7/ AN768 VDDA69 VRH70 VRL71 VSSA72 VSS173 VDD174PT7/ TIM_ IOC775PT6/ TIM_ IOC676PT5/ TIM_ IOC577PT4/ TIM_ IOC478PJ7/ KWJ7/ IIC_ SCL79PJ6/ KWJ6/ IIC_SDA80 ECLK/PE429 LED5 COL_LEDR9220R1 2220 LED4 ACT_LEDPL4/COLLEDPL0/ACTLEDOPTIONAL STATUS LED's75 OHMS75 OHMS1000 pF2kVCABLE SIDEMCU SIDET1 TRANSFORMER / RJ-45

10 CONNECTORT+1CT2T-3R+ OHMS75 OHMS1000 pF2kVCABLE SIDEMCU SIDET1 TRANSFORMER / RJ-45 CONNECTORT+1CT2T-3R+ 3VJ1 BACKGROUND DEBUG113355224466* 1%PL1/LNKLEDPL3/DUPLEDPL2/SPDLED3. 3V3. 3V* .22PL0/ACTLEDPL4/ COLLEDLED3 DUP_L EDR7220 LED1 LNK_LEDR6220R8220 LED2 SPD_LEDY125 RXD/ PS021 SCI0_ TXD/ PS122 SCI1_ RXD/ PS223 SCI1_ TXD/ PS324 SPI_ MISO/ PS425 SPI_ MOSI/ PS526 SPI_ SCK/ PS627 SPI_SS/ PS728 VSSX230 VDDX231 RESET32 VDDPLL33 XFC34 VSSPLL35 EXTAL36 XTAL37 TEST38 IRQ/ PE139 XIRQ/ PE040 BKGD/MODC41PL4/COLLED42PL3/DUPLED43 VSS244 VDD245 PHY_RBIAS46 PHY_VSSA47 PHY_VDDA48 PHY_VDDTX49 PHY_TXP50 PHY_TXN51 PHY_VSSTX52 PHY_RXP53 PHY_RXN54 PHY_VDDRX55 PHY_VSSRX56PL2/SPDLED57 VDDR58PL1/LNKLED59PL0/ACTLED60 PAD0/ AN061 PAD1/ AN162 PAD2/ AN263 PAD3/ AN364 MII_COL/KWJ3/PJ313 MII_RXD0/KWG0/PG014 MII_RXD1/KWG1/PG115 MII_RXD2/KWG2/PG216 MII_RXD3/KWG3/PG317 MII_RXCLK/KWG4/PG418 MII_RXDV/KWG5/PG519 MII_RXER/KWG6/PG620 SCI0_ RXD/ PS021 SCI0_ TXD/ PS122 SCI1_ RXD/ PS223 SCI1_ TXD/ PS324 SPI_ MISO/ PS425 SPI_ MOSI/ PS526 SPI_ SCK/ PS627 SPI_SS/ PS728 VSSX230 VDDX231 RESET32 VDDPLL33 XFC34 VSSPLL35 EXTAL36