ARMv7-M Architecture Reference Manual

1 Copyright 2006-2010 ARM limited . All rights DDI 0403C_errata_v3 (ID021910)ARM v7-M ArchitectureReference Manual iiCopyright 2006-2010 ARM limited . All rights DDI 0403C_errata_v3 Non-Confidential, Unrestricted AccessID021910 ARMv7-M Architecture Reference ManualCopyright 2006-2010 ARM limited . All rights InformationThe following changes have been made to this NoticeThis ARM Architecture Reference Manual is protected by copyright and the practice or implementation of the information herein may be protected by one or more patents or pending applications. No part of this ARM Architecture Reference Manual may be reproduced in any form by any means without the express prior written permission of ARM. No license, express or implied, by estoppel or otherwise to any intellectual property rights is granted by this ARM Architecture Reference access to the information in this ARM Architecture Reference Manual is conditional upon your acceptance that you will not use or permit others to use the information for the purposes of determining whether implementations of the ARM Architecture infringe any third party ARM Architecture Reference Manual is provided as is.

2 ARM makes no representations or warranties, either express or implied, included but not limited to, warranties of merchantability, fitness for a particular purpose, or non-infringement, that the content of this ARM Architecture Reference Manual is suitable for any particular purpose or that any practice or implementation of the contents of the ARM Architecture Reference Manual will not infringe any third party patents, copyrights, trade secrets, or other ARM Architecture Reference Manual may include technical inaccuracies or typographical the extent not prohibited by law, in no event will ARM be liable for any damages, including without limitation any direct loss, lost revenue, lost profits or data, special, indirect, consequential, incidental or punitive damages, however caused and regardless of the theory of liability, arising out of or related to any furnishing, practicing, modifying or any use of this ARM Architecture Reference Manual , even if ARM has been advised of the possibility of such and logos marked with or are registered trademarks or trademarks of ARM limited , except as otherwise stated below in this proprietary notice.

3 Other brands and names mentioned herein may be the trademarks of their respective 2006-2010 ARM Limited110 Fulbourn Road Cambridge, England CB1 9 NJChange historyDateIssueConfidentialityChangeJun e 2006 ANon-confidentialInitial releaseJuly 2007 BNon-confidentialSecond release, errata and changes documented separatelySeptember 2008 CNon-confidential, Restricted AccessOptions for additional watchpoint based trace in the DWT, plus errata updates and 2009C_errataNon-confidentialMarked-up errata PDF, see page iii for more 2010C_errata_v3 Non-confidentialAdditional marked-up errata PDF, see page iii for more information. ARM DDI 0403C_errata_v3 Copyright 2006-2010 ARM limited . All rights , Unrestricted AccessRestricted Rights Legend: Use, duplication or disclosure by the United States Government is subject to the restrictions set forth in DFARS (c)(1)(ii) and FAR document is Non-Confidential but any disclosure by you is subject to you providing notice to and the acceptance by the recipient of, the conditions set out this document, where the term ARM is used to refer to the company it means ARM or any of its subsidiaries as appropriate.

4 Note The term ARM is also used to refer to versions of the ARM Architecture , for example ARMv6 refers to version 6 of the ARM Architecture . The context makes it clear when the term is used in this This errata PDF is regenerated from the source files of issue C of this document, but: Some pseudocode examples, that are imported into the document, have been updated. Markups highlight significant changes in these pseudocode pseudocode updates are made using the standard Acrobat editing tools. Pages ii and iii of the PDF have been replaced, by an edit to the PDF, to include an updated Proprietary these exceptions, this PDF corresponds to the released PDF of issue C of the document, with errata indicated by markups to the PDF: the original errata markups, issued June 2009, are identified as ARM_2009_Q2 additional errata markups, issued February 2010, are identified as ARM_2009_Q4. In the revised pseudocode, the function BadReg(x) is replaced by a new construct, x IN {13,15}, that can be used in other contexts.

5 This is a format change only. From February 2010, issue C of the ARMv7-M ARM is superseded by issue D of the document. ARM strongly recommends you to use issue D of the document in preference to using this errata PDF. ivCopyright 2006-2010 ARM limited . All rights DDI 0403C_errata_v3 Non-Confidential, Unrestricted AccessID021910 ARM DDI 0403 CCopyright 2006-2008 ARM limited . All rights AccessNon-ConfidentialContentsARMv7-M Architecture Reference ManualPrefaceAbout this Manual .. xviiiUsing this Manual .. xixConventions .. xxiiFurther reading .. xxiiiFeedback .. xxivPart AApplication Level ArchitectureChapter ARM Architecture M profile .. A1-2 Chapter A2 Application Level Programmers the Application level programmers model .. core data types and arithmetic .. and execution state .. , faults and interrupts .. support .. A2-16 Chapter A3 ARM Architecture Memory space .. A3-2 ContentsviCopyright 2006-2008 ARM limited . All rights DDI 0403 CNon-ConfidentialRestricted support.

6 Support .. and semaphores .. types and attributes and the memory order model .. rights .. access order .. and memory hierarchy .. A3-38 Chapter A4 The ARMv7-M Instruction the instruction set .. Assembler Language .. instructions .. instructions .. register access instructions .. and store instructions .. multiple instructions .. instructions .. instructions .. instructions .. A4-22 Chapter A5 Thumb Instruction Set instruction set encoding .. Thumb instruction encoding .. Thumb instruction encoding .. A5-13 Chapter A6 Thumb Instruction of instruction descriptions .. assembler syntax fields .. execution .. applied to a register .. accesses .. Instructions .. list of ARMv7-M Thumb instructions .. A6-17 Part BSystem Level ArchitectureChapter B1 System Level Programmers to the system level .. : a memory mapped Architecture .. level operation and terminology overview .. model.

7 B1-14 Chapter B2 System Memory .. B2-2 ContentsARM DDI 0403 CCopyright 2006-2008 ARM limited . All rights details of general memory system operations .. B2-3 Chapter B3 System Address system address map .. Control Space (SCS) .. timer - SysTick .. Vectored Interrupt Controller (NVIC) .. Memory System Architecture (PMSAv7) .. B3-35 Chapter B4 ARMv7-M System list of ARMv7-M system instructions .. B4-2 Part CDebug ArchitectureChapter C1 ARMv7-M to debug .. Debug Access Port (DAP) .. of the ARMv7-M debug features .. and reset .. event behavior .. register support in the SCS .. Trace Macrocell (ITM) support .. Watchpoint and Trace (DWT) support .. Trace (ETM) support .. Port Interface Unit (TPIU) .. Patch and Breakpoint (FPB) support .. C1-61 Appendix Feature ID Registers .. Feature register0 (ID_PFR0) .. Feature register1 (ID_PFR1) .. Features register0 (ID_DFR0) .. Features register0 (ID_AFR0).

8 Model Feature registers .. Set Attribute registers background information .. Set Attribute registers details .. AppxA-12 Appendix BARMv7-M infrastructure IDsAppendix CLegacy Instruction instruction mnemonics .. pseudo-instruction NOP .. AppxC-6 ContentsviiiCopyright 2006-2008 ARM limited . All rights DDI 0403 CNon-ConfidentialRestricted AccessAppendix DDeprecated Features in ARMv7-MAppendix EDebug ITM and DWT packet Types .. packet formats .. AppxE-8 Appendix FARMv7-R support .. level support .. level support .. support .. AppxF-5 Appendix GPseudocode encoding diagrams and pseudocode .. of pseudocode .. Types .. and built-in functions .. and program structure .. helper procedures and functions .. AppxG-22 Appendix HPseudocode operators and keywords .. functions and procedures .. AppxH-5 Appendix IRegister core registers .. mapped system registers .. mapped debug registers .. AppxI-5 GlossaryARM DDI 0403 CCopyright 2006-2008 ARM limited .

9 All rights AccessNon-ConfidentialList of TablesARMv7-M Architecture Reference ManualChange History .. iiTable A3-1 Little-endian byte format .. A3-5 Table A3-2 Big-endian byte format .. A3-5 Table A3-3 Little-endian memory system .. A3-6 Table A3-4 Big-endian memory system .. A3-6 Table A3-5 Load-store and element size association .. A3-7 Table A3-6 Effect of Exclusive instructions and write operations on local monitor .. A3-10 Table A3-7 Effect of load/store operations on global monitor for processor(n) .. A3-14 Table A3-8 Memory attribute summary .. A3-19 Table A4-1 Branch instructions .. A4-7 Table A4-2 Standard data-processing instructions .. A4-9 Table A4-3 Shift instructions .. A4-10 Table A4-4 General multiply instructions .. A4-11 Table A4-5 Signed multiply instructions .. A4-11 Table A4-6 Unsigned multiply instructions .. A4-11 Table A4-7 Core saturating instructions .. A4-12 Table A4-8 Packing and unpacking instructions .. A4-13 Table A4-9 Miscellaneous data-processing instructions.

10 A4-14 Table A4-10 Load and store instructions .. A4-16 Table A4-11 Load/store multiple instructions .. A4-19 Table A4-12 Miscellaneous instructions .. A4-20 Table A5-116-bit Thumb instruction encoding .. A5-5 Table A5-216-bit shift(immediate), add, subtract, move and compare encoding .. A5-6 List of TablesxCopyright 2006-2008 ARM limited . All rights DDI 0403 CNon-ConfidentialRestricted AccessTable A5-316-bit data processing instructions .. A5-7 Table A5-4 Special data instructions and branch and exchange .. A5-8 Table A5-516-bit Load/store instructions .. A5-9 Table A5-6 Miscellaneous 16-bit instructions .. A5-10 Table A5-7If-Then and hint instructions .. A5-11 Table A5-8 Branch and supervisor call instructions .. A5-12 Table A5-932-bit Thumb encoding .. A5-13 Table A5-1032-bit modified immediate data processing instructions .. A5-14 Table A5-11 Encoding of modified immediates in Thumb data-processing instructions .. A5-15 Table A5-1232-bit unmodified immediate data processing instructions.