Arria V Device Handbook - Altera

1 Arria V Device Handbook Volume 1: Device Interfaces and Integration Subscribe AV-5V2 101 Innovation Drive San Jose, CA 95134. Send Feedback TOC-2 Arria V Device Handbook Volume 1: Device Interfaces and Integration Contents Logic Array Blocks and Adaptive Logic Modules in Arria V 1-1. LAB .. 1-1. MLAB .. 1-2. Local and Direct Link Interconnects .. 1-4. LAB Control 1-5. ALM Resources .. 1-7. ALM Output .. 1-9. ALM Operating Modes .. 1-11. Normal Mode .. 1-11. Extended LUT Mode .. 1-12. Arithmetic Mode ..1-12. Shared Arithmetic Mode ..1-13. Logic Array Blocks and Adaptive Logic Modules in Arria V devices Revision 1-15. Embedded Memory Blocks in Arria V 2-1. Types of Embedded 2-1. Embedded Memory Capacity in Arria V 2-2. Embedded Memory Design Guidelines for Arria V Guideline: Consider the Memory Block 2-2. Guideline: Implement External Conflict Guideline: Customize Read-During-Write 2-3. Guideline: Consider Power-Up State and Memory 2-7. Guideline: Control Clocking to Reduce Power Embedded Memory 2-7.

2 Embedded Memory Mixed-Width Port 2-10. Embedded Memory 2-12. Embedded Memory Clocking 2-14. Clocking Modes for Each Memory 2-14. Asynchronous Clears in Clocking 2-15. Output Read Data in Simultaneous Independent Clock Enables in Clocking Parity Bit in Memory Byte Enable in Embedded Memory 2-16. Byte Enable Controls in Memory 2-16. Data Byte 2-16. RAM Blocks 2-17. Memory Blocks Packed Mode Memory Blocks Address Clock Enable 2-17. Memory Blocks Error Correction Code 2-19. Error Correction Code Truth Embedded Memory Blocks in Arria V devices Revision 2-20. Altera Corporation Arria V Device Handbook Volume 1: Device Interfaces and Integration TOC-3. Variable Precision DSP Blocks in Arria V Supported Operational Modes in Arria V 3-2. Design 3-5. Operational 3-5. Internal Coefficient and 3-6. 3-6. Chainout Block 3-7. Input Register 3-11. Internal 3-17. 3-17. 3-17. Accumulator and Chainout 3-18. Systolic 3-18. Double Accumulation 3-19. Output Register 3-19. Operational Mode 3-19.

3 Independent Multiplier 3-19. Independent Complex Multiplier 3-27. Multiplier Adder Sum 3-33. Sum of Square 18 x 18 Multiplication Summed with 36-Bit Input Systolic FIR 3-39. Variable Precision DSP Blocks in Arria V devices Revision Clock Networks and PLLs in Arria V 4-1. Clock 4-1. Clock Resources in Arria V Types of Clock 4-3. Clock Sources Per Types of Clock 4-7. Clock Network 4-8. Clock Output Clock Control 4-11. Clock Power 4-14. Clock Enable Arria V 4-16. PLL Physical Counters in Arria V PLL Locations in Arria V 4-17. PLL Migration Guidelines .. 4-22. Fractional PLL 4-23. PLL PLL External Clock I/O 4-24. Altera Corporation TOC-4 Arria V Device Handbook Volume 1: Device Interfaces and Integration PLL Control 4-25. Clock Feedback Clock Multiplication and 4-32. Programmable Phase Programmable Duty Clock PLL Reconfiguration and Dynamic Phase 4-38. Clock Networks and PLLs in Arria V devices Revision 4-38. I/O Features in Arria V 5-1. I/O Resources Per Package for Arria V 5-1.

4 I/O Vertical Migration for Arria V 5-4. Verifying Pin Migration I/O Standards Support in Arria V I/O Standards Support for FPGA I/O in Arria V I/O Standards Support for HPS I/O in Arria V I/O Standards Voltage Levels in Arria V 5-8. MultiVolt I/O Interface in Arria V I/O Design Guidelines for Arria V Mixing Voltage-Referenced and Non-Voltage-Referenced I/O Guideline: Use the Same VCCPD for All I/O Banks in a Guideline: Ensure Compatible VCCIO and VCCPD Voltage in the Same 5-13. Guideline: VREF Pin 5-13. Guideline: Observe Device Absolute Maximum Rating for V 5-13. Guideline: Use PLL Integer Mode for LVDS 5-14. Guideline: Pin Placement for General Purpose High-Speed 5-14. I/O Banks Locations in Arria V 5-14. I/O Banks Groups in Arria V 5-17. Modular I/O Banks for Arria V GX Modular I/O Banks for Arria V GT Modular I/O Banks for Arria V GZ Modular I/O Banks for Arria V SX Modular I/O Banks for Arria V ST 5-23. I/O Element Structure in Arria V 5-23. I/O Buffer and Registers in Arria V 5-24.

5 Programmable IOE Features in Arria V 5-26. Programmable Current 5-28. Programmable Output Slew Rate Programmable IOE Programmable Output Buffer 5-30. Programmable Programmable Differential Output 5-31. Open-Drain Pull-up 5-33. Bus-Hold 5-33. On-Chip I/O Termination in Arria V 5-33. RS OCT without Calibration in Arria V RS OCT with Calibration in Arria V 5-36. Altera Corporation Arria V Device Handbook Volume 1: Device Interfaces and Integration TOC-5. RT OCT with Calibration in Arria V 5-38. Dynamic OCT in Arria V 5-40. LVDS Input RD OCT in Arria V 5-41. OCT Calibration Block in Arria V External I/O Termination for Arria V 5-45. Single-ended I/O 5-46. Differential I/O 5-48. I/O Features in Arria V devices Revision 5-54. High-Speed Differential I/O Interfaces and DPA in Arria V Dedicated High-Speed Circuitries in Arria V 6-2. SERDES and DPA Bank Locations in Arria V 6-2. LVDS SERDES True LVDS Buffers in Arria V Emulated LVDS Buffers in Arria V High-Speed I/O Design Guidelines for Arria V PLLs and Clocking for Arria V LVDS Interface with External PLL 6-8.

6 Pin Placement Guidelines for DPA and Non-DPA Differential 6-13. Differential Transmitter in Arria V Transmitter 6-21. Transmitter Serializer Bypass for DDR and SDR 6-23. Programmable Differential Output 6-23. Programmable Differential Receiver in Arria V 6-25. Receiver Blocks in Arria V 6-26. Receiver Modes in Arria V Receiver Clocking for Arria V 6-32. Differential I/O Termination for Arria V Source-Synchronous Timing Differential Data 6-34. Differential I/O Bit Transmitter Channel-to-Channel 6-36. Receiver Skew Margin for Non-DPA 6-36. High-Speed Differential I/O Interfaces and DPA in Arria V devices Revision External Memory Interfaces in Arria V External Memory HPS External Memory Memory Interface Pin Support in Arria V Guideline: Using DQ/DQS DQ/DQS Bus Mode Pins for Arria V 7-4. DQ/DQS Groups in Arria V DQ/DQS Groups in Arria V DQ/DQS Groups in Arria V DQ/DQS Groups in Arria V Altera Corporation TOC-6 Arria V Device Handbook Volume 1: Device Interfaces and Integration DQ/DQS Groups in Arria V External Memory Interface Features in Arria V 7-10.

7 UniPHY 7-10. External Memory Interface 7-10. DQS Phase-Shift PHY Clock (PHYCLK) DQS Logic 7-23. Leveling Circuitry for Arria V GZ 7-26. Dynamic OCT 7-28. IOE 7-28. Delay I/O and DQS Configuration 7-34. Hard Memory Features of the Hard Memory 7-35. Multi-Port Front End ..7-37. Bonding 7-37. Hard Memory Controller Width for Arria V Hard Memory Controller Width for Arria V 7-41. Hard Memory Controller Width for Arria V 7-42. Hard Memory Controller Width for Arria V 7-42. External Memory Interfaces in Arria V devices Revision Configuration, Design Security, and Remote System Upgrades in Arria V. 8-1. Enhanced Configuration and Configuration via 8-1. MSEL Pin Configuration Power 8-6. 8-6. 8-7. Configuration Error 8-7. User 8-7. Configuration Timing FPP Configuration 8-8. AS Configuration 8-10. PS Configuration Device Configuration I/O Standards and Drive Strength for Configuration Configuration Pin Options in the Intel Quartus Prime Fast Passive Parallel Fast Passive Parallel Single- Device 8-15.

8 Fast Passive Parallel Multi- Device 8-16. Transmitting Configuration 8-18. Active Serial 8-19. DATA Clock (DCLK).. 8-19. Active Serial Single- Device 8-20. Active Serial Multi- Device 8-21. Altera Corporation Arria V Device Handbook Volume 1: Device Interfaces and Integration TOC-7. Estimating the Active Serial Configuration 8-23. Using EPCS and EPCQ Controlling EPCS and EPCQ 8-24. Trace Length and Loading 8-24. Programming EPCS and EPCQ 8-24. Passive Serial Passive Serial Single- Device Configuration Using an External Passive Serial Single- Device Configuration Using an Altera Download Passive Serial Multi- Device JTAG 8-33. JTAG Single- Device 8-34. JTAG Multi- Device 8-35. CONFIG_IO JTAG 8-36. Configuration Data Enabling Compression Before Design 8-37. Enabling Compression After Design Using Compression in Multi- Device Remote System Configuration Configuration Sequence in the Remote Update 8-40. Remote System Upgrade 8-40. Enabling Remote System Upgrade 8-41. Remote System Upgrade 8-42.

9 Remote System Upgrade State 8-43. User Watchdog 8-43. Design Altera Unique Chip ID IP JTAG Secure Security Key 8-45. Security 8-46. Design Security Implementation 8-47. Configuration, Design Security, and Remote System Upgrades in Arria V devices Revision 8-47. SEU Mitigation for Arria V 9-1. Error Detection Configuration Error User Mode Error 9-1. 9-2. Minimum EMR Update Error Detection 9-3. CRC Calculation Time For Entire 9-3. Using Error Detection Features in User Enabling Error CRC_ERROR Error Detection Error Detection 9-8. Testing the Error Detection 9-9. Altera Corporation TOC-8 Arria V Device Handbook Volume 1: Device Interfaces and Integration SEU Mitigation for Arria V devices Revision 9-10. JTAG Boundary-Scan Testing in Arria V 10-1. BST Operation Control .. 10-1. IDCODE ..10-1. Supported JTAG Instruction .. 10-3. JTAG Secure Mode ..10-7. JTAG Private Instruction .. 10-7. I/O Voltage for JTAG Operation ..10-8. Performing BST ..10-8. Enabling and Disabling IEEE Std.

10 BST Circuitry ..10-9. Guidelines for IEEE Std. Boundary-Scan 10-10. IEEE Std. Boundary-Scan Register .. 10-10. Boundary-Scan Cells of an Arria V Device I/O 10-11. IEEE Std. Boundary-Scan 10-13. JTAG Boundary-Scan Testing inArria V devices Revision Power Management in Arria V 11-1. Power 11-1. Dynamic Power 11-2. Programmable Power Temperature Sensing 11-3. Internal Temperature Sensing 11-4. External Temperature Sensing Hot-Socketing Hot-Socketing 11-6. Arria V GX, GT, SX, and ST Power-Up Arria V GZ Power-Up Power-On Reset Power Supplies Monitored and Not Monitored by the POR Power Management in Arria V devices Revision Altera Corporation Logic Array Blocks and Adaptive Logic Modules in Arria V devices 1. AV-52001 Subscribe Send Feedback This chapter describes the features of the logic array block (LAB) in the Arria V core fabric. The LAB is composed of basic building blocks known as adaptive logic modules (ALMs) that you can configure to implement logic functions, arithmetic functions, and register functions.